Publication List of Pin Su

(A) Refereed Journal Papers and Book Chapters

1.      W.-X. You and Pin Su, "Intrinsic Difference between 2D Negative-Capacitance FETs with Semiconductor-on-Insulator and Double-Gate Structures,” IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4196-4201, October 2018.

2.      M.-H. Lin, Pin Su, H.-Y. Chen, J.-H. Lu, V. S. Chang, S.-H. Yang, "Experimental Analysis of Quasi-Ballistic Transport in Advanced Si nFinFETs using New Extraction Method," IEEE Electron Device Letters, vol. 39, no. 9, pp. 1397-1400, September 2018.

3.      W.-X. You, C.-P. Tsai, and Pin Su, "Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors,” IEEE Transactions on Electron Devices, vol. 65, no. 4, pp. 1604-1610, April 2018.

4.      H.-P. Lee and Pin Su, "Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs," IEEE Electron Device Letters, vol. 38, no. 10, pp. 1492-1495, October 2017.

5.      W.-X. You and Pin Su, "Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors,” IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3476-3481, August 2017.

6.      C.-H. Yu, Pin Su and C.-T. Chuang, "Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells with Mono- and Few-Layer Transition Metal Dichalcogenide (TMD) MOSFETs," IEEE Transactions on Electron Devices, vol. 64, no. 5, pp. 2445-2451, May 2017.

7.      S.-H. Wu, C.-L. Yu, C.-H. Yu, and Pin Su, "Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs including Sensitivity to Process Variations," IEEE Journal of the Electron Devices Society, vol. 5, no. 1, pp. 45-52, January 2017.

8.      W.-X. You and Pin Su, "A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2971-2974, July 2016.

9.      C.-H. Yu, Pin Su and C.-T. Chuang, "Impact of Random Variations on Cell Stability and Write-ability of Low-Voltage SRAMs using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs," IEEE Electron Device Letters, vol. 37, no. 7, pp. 928-931, July 2016.

10.   M.-L. Fan, Y.-N. Chen, Pin Su and C.-T. Chuang, "Challenges and Designs of TFET for Digital Applications," in Tunneling Field Effect Transistor Technology, pp. 89-109, Springer International Publishing, April 2016.

11.   K.-C. Yu, M.-L. Fan, Pin Su and C.-T. Chuang, "Evaluation of Monolithic 3D Logic Circuits and 6T SRAMs with InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs," IEEE Journal of the Electron Devices Society, vol. 4, no. 2, pp. 76-82, March 2016.

12.   C.-H. Yu, M.-L. Fan, K.-C. Yu, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Evaluation of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Devices for SRAM Applications," IEEE Transactions on Electron Devices, vol. 63, no. 2, pp. 625-630, February 2016.

13.   H.-H. Shen, S.-L. Shen, C.-H. Yu, and Pin Su, "Impact of Quantum Capacitance on Intrinsic Inversion Capacitance Characteristics and Inversion-Charge Loss for Multi-Gate III-V-on-Insulator n-MOSFETs," IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 339-344, January 2016.

14.   S.-H. Wu, C.-H. Yu, and Pin Su, "New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs," IEEE Journal of the Electron Devices Society, vol. 3, no. 6, pp. 441-446, November 2015.

15.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Analysis of GeOI FinFET 6T SRAM Cells with Variation-Tolerant WLUD Read-Assist and TVC Write-Assist," IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 1710-1715, June 2015.

16.      C.-W. Hsu, M.-L. Fan, V. P.-H. Hu, and Pin Su, "Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET," IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 194-199, May 2015.

17.      Y.-N. Chen, C.-J. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits," Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp. 101-115, May 2015.

18.   K.-C. Lee, M.-L. Fan, and Pin Su, "Investigation and Comparison of Analog Figures-of-Merit for TFET and FinFET Considering Work-Function Variation," Microelectronics Reliability, vol. 55, issue 2, pp. 332–336, February 2015.

19.   S.-H. Wu, C.-H. Yu, C.-H. Chiang, and Pin Su, "Investigation of Multi-Vth Efficiency for Trigate GeOI p-MOSFETs Using Analytical Solution of 3-D Poisson’s Equation," IEEE Transactions on Electron Devices, vol. 62, no. 1, pp. 88-93, January 2015.

20.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, C.-W. Hsu, Pin Su and C.-T. Chuang, "Investigation of Backgate-Biasing Effect for Ultra-Thin-Body III-V Heterojunction Tunnel FET," IEEE Transactions on Electron Devices, vol. 62, no. 1, pp. 107-113, January 2015.

21.   Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET and Mixed TFET-MOSFET SRAM Cell with Write-Assist Circuits," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, no. 4, pp. 389-399, December 2014.

22.   Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Evaluation of Sub-0.2V High-Speed Low-Power Circuits using Hetero-Channel MOSFET and Tunneling FET Devices," IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 61, no. 12, 3339-3347, December 2014.

23.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Stability and Performance Optimization of Hetero-Channel Monolithic 3D SRAM Cells Considering Interlayer Coupling," IEEE Transactions on Electron Devices, vol. 61, no. 10, pp. 3448-3455, October 2014.

24.   C.-H. Yu and Pin Su, "Built-in Effective Body-Bias Effect in Ultra-Thin-Body Hetero-Channel III-V-on-Insulator n-MOSFETs," IEEE Electron Device Letters, vol. 35, no. 8, pp. 823-825, August 2014.

25.   C.-W. Yang and Pin Su, "Simulation and Investigation of Random Grain-Boundary-Induced Variabilities for Stackable NAND Flash Using 3D-Voronoi Grain Patterns," IEEE Transactions on Electron Devices, vol. 61, no. 4, pp. 1211-1214, April 2014.

26.   M.-L. Fan, S.-Y. Yang, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Single-Trap-Induced Random Telegraph Noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and Logic Circuits," Microelectronics Reliability (Invited), vol. 54, issue 4, pp. 698–711, April 2014.

27.   C.-H. Yu and Pin Su, "Investigation of Backgate-Bias Dependence of Threshold-Voltage Sensitivity to Process and Temperature Variations for Ultra-Thin-Body Hetero-Channel MOSFETs," IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, pp. 375-381, March 2014.

28.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET," IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3596-3600, October 2013.

29.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Threshold Voltage Design of UTB SOI SRAM with Improved Stability/Variability for Ultra-Low Voltage near Subthreshold Operation," IEEE Transactions on Nanotechnology, vol. 12, no. 4, pp. 524-531, July 2013.

30.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Analysis of Single-Trap-Induced Random Telegraph Noise and Its Interaction with Work Function Variation for Tunnel FET," IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 2038-2044, June 2013.

31.   S.-H. Chou, M.-L. Fan, and Pin Su, "Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using Voronoi Approach," IEEE Transactions on Electron Devices, vol. 60, no. 4, pp. 1485-1489, April 2013.

32.   Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Design and Analysis of Robust Tunneling FET SRAM," IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 1092-1098, March 2013.

33.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Threshold Voltage Design and Performance Assessment of Hetero-channel SRAM Cells," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 147-152, January 2013.

34.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications," IEEE Transactions on Circuits and Systems - II: Express Briefs, vol. 59, no. 12, pp. 878-882, December 2012.

35.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Analysis of Single Trap Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell and Logic Circuits," IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2227-2234, August 2012.

36.   C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and Pin Su, "Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETs," IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1851-1855, July 2012.

37.   C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 7, pp. 1201-1210, July 2012.

38.   Y.-S. Wu and Pin Su, "A Closed-Form Quantum "Dark Space" Model for Predicting the Electrostatic Integrity of Germanium MOSFETs with High-k Gate Dielectric," IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 530-535, March 2012.

39.   S.-C. Wang, Pin Su, K.-M. Chen, B.-Y. Chen, G.-W. Huang, "Investigation of Temperature-Dependent High-Frequency Noise Characteristics for Deep-Submicron Bulk and SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 551-556, March 2012.

40.   C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and Pin Su, "Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs," IEEE Transactions on Nanotechnology, vol. 11, no. 2, pp. 287-291, March 2012.

41.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Band-to-Band Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs using Transistor Stacking," IEEE Electron Device Letters, vol. 33, no. 2, pp. 197-199, February 2012.

42.   W. P.-N. Chen, J. J.-Y. Kuo, and Pin Su, "Enhanced Temperature Dependence of Phonon-Scattering Limited Mobility in Compressively Uniaxial Strained PMOSFETs," IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4427-4429, December 2011. 

43.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation and Temperature Sensitivity," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp. 335-342, September 2011. 

44.   V. P.-H. Hu, Y.-S. Wu, and Pin Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body Germanium-On-Nothing (GeON) MOSFET," IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 325-330, March 2011.  

45.   V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, Pin Su and C.-T. Chuang, "FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics," IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 805-811, March 2011.  

46.   J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Temperature Dependence of Drain Current Mismatch in Nanoscale Uniaxial-Strained PMOSFETs," IEEE Electron Device Letters, vol. 32, no. 3, pp. 240-242, March 2011.  

47.   M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, C.-Y. Hsieh, Pin Su and C.-T. Chuang, "Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability – A Model-Based Approach," IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 609-616, March 2011. 

48.   S.-C. Wang, Pin Su, K. Chen, B. Chen, G.-W. Huang, C. Hung, S. Huang, C. Fan, C. Tzeng, S. Chou, "Investigation of High Frequency Noise Characteristics in Tensile-Strained nMOSFETs," IEEE Transactions on Electron Devices, vol 58, no. 3, pp. 895-900, March 2011. 

49.   W. P.-N. Chen, J. J.-Y. Kuo, and Pin Su, "Experimental Investigation of Surface Roughness Limited Mobility in Uniaxial Strained pMOSFETs," IEEE Electron Device Letters, vol. 32, no. 2, pp. 113-115, February 2011. 

50.   Y.-S. Wu, H.-Y. Hsieh, V. P.-H. Hu, and Pin Su, "Impact of Quantum Confinement on Short-Channel Effects for Ultra-Thin-Body Germanium-On-Insulator MOSFETs," IEEE Electron Device Letters, vol. 32, no. 1, pp. 18-20, January 2011. 

51.   Y.-S. Wu and Pin Su, “Impact of Surface Orientation on the Sensitivity of FinFETs to Process Variation – An Assessment Based on Analytical Solution of Schrödinger Equation,” IEEE Transactions on Electron Devices, vol. 57, no. 12, pp. 3312-3317, December 2010. 

52.   S.-C. Wang, Pin Su, K. Chen, K. Liao, B. Chen, S. Huang, C. Hung, G.-W. Huang, "Temperature-Dependent RF Small-Signal and Noise Characteristics of SOI Dynamic Threshold Voltage MOSFETs," IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 9, pp. 2319-2325, September 2010. 

53.   M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Investigation of Cell Stability and Write-ability of FinFET Subthreshold SRAM using Analytical SNM Model," IEEE Transactions on Electron Devices, vol. 57, no. 6, pp. 1375-1381, June 2010. 

54.   W. P.-N. Chen, J. J.-Y. Kuo, and Pin Su, "Impact of Process-Induced Uniaxial Strain on the Temperature Dependence of Carrier Mobility in Nanoscale pMOSFETs," IEEE Electron Device Letters, vol. 31, no. 5, pp. 414-416, May 2010. 

55.   J. J.-Y Kuo, W. P.-N. Chen, and Pin Su, "Enhanced Carrier-Mobility-Fluctuation Origin Low Frequency Noise in Uniaxial Strained PMOSFETs," IEEE Electron Device Letters, vol. 31, no. 5, pp. 497-499, May 2010. 

56.   S.-C. Wang, Pin Su, K. Chen, K. Liao, B. Chen, S. Huang, C. Hung, G.-W. Huang, "Comprehensive Noise Characterization and Modeling for 65nm MOSFETs for Millimeter-Wave Applications," IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 4, pp. 740-746, April 2010. 

57.   J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs," IEEE Transactions on Nanotechnology, vol. 9, no. 2, pp. 248-253, March 2010.   

58.   Y.-S. Wu, M.-L. Fan, and Pin Su, "Investigation of Switching Time Variations for Nanoscale MOSFETs Using the Effective Drive Current Approach," IEEE Electron Device Letters, vol. 31, no. 2, pp. 162-164, February 2010.  

59.   W. Lee and Pin Su, "Investigation of Channel Backscattering Characteristics in Nanoscale Uniaxial Strained PMOSFETs," IEEE Transactions on Nanotechnology, vol. 8, no. 6, pp. 692-696, November 2009.  

60.   Y.-S. Wu and Pin Su, "Analytical Quantum Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold Region," IEEE Transactions on Electron Devices, vol. 56, no. 11, pp. 2720-2725, November 2009.  

61.   W. Lee and Pin Su, "On the Experimental Determination of Channel Backscattering Characteristics - Limitation and Application for the Process Monitoring Purpose," IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 2285-2290, October 2009.  

62.   V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, Pin Su and C.-T. Chuang, "Static Noise Margin of Ultra-Thin-Body SOI Subthreshold SRAM Cells - An Assessment Based on Analytical Solution of Poisson's Equation," IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 2120-2127, September 2009.  

63.   W. Lee and Pin Su, "A Comparative Study of Carrier Transport for Overlapped and Non-overlapped Multiple-Gate SOI MOSFETs," IEEE Transactions on Nanotechnology, vol. 8, no. 4, pp. 444-448, July 2009.  

64.   J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Impact of Uniaxial Strain on Low Frequency Noise in Nanoscale PMOSFETs," IEEE Electron Device Letters, vol. 30, no. 6, pp. 672-674, June 2009.   

65.   V. P.-H. Hu, Y.-S. Wu and Pin Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body GeOI MOSFET Using Analytical Solution of Poisson’s Equation," Semiconductor Science and Technology, vol. 24, no. 4, April 2009.  

66.   S.-C. Wang, Pin Su, K. Chen, S. Huang, C. Hung, G.-W. Huang, "Radio-Frequency Small-Signal and Noise Modeling for Silicon-on-Insulator Dynamic Threshold Voltage Metal–Oxide– Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 48, no. 4, April 2009. 

67.   W. Lee and Pin Su, "Single-electron effects in non-overlapped multiple-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors," Nanotechnology, vol. 20, no. 6, February 2009.  

68.   J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs," IEEE Transactions on Electron Devices, vol. 56, no. 2, pp. 284-290, February 2009.   

69.   W. P.-N. Chen, Pin Su, K. Goto, C. Diaz, "Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs," Journal of The Electrochemical Society, vol. 156, issue 1, H34-H38, 2009. 

70.   Y.-S. Wu and Pin Su, "Sensitivity of Gate-All-Around Nanowire MOSFETs to Process Variations - A Comparison with Multi-Gate MOSFETs," IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3042-3047, November 2008.    

71.   W. P.-N. Chen, Pin Su, K. Goto, "Investigation of Coulomb Mobility in Nanoscale Strained PMOSFETs," IEEE Transactions on Nanotechnology, vol. 7, no. 5, pp. 538-543, September 2008.  

72.   S.-C. Wang, Pin Su, K. Chen, C. Lin, V. Liang, G.-W. Huang, "Temperature Dependence of High Frequency Noise Behaviors for RF MOSFETs," IEEE Microwave and Wireless Components Letters, vol. 18, no. 8, pp. 530-532, August 2008. 

73.   W. P.-N. Chen, Pin Su, K. Goto, "Impact of Process-Induced Strain on Coulomb Scattering Mobility in Short-Channel n-MOSFETs," IEEE Electron Device Letters, vol. 29, no. 7, pp. 768-770, July 2008.  

74.   Y.-S. Wu and Pin Su, "Sensitivity of Multi-Gate MOSFETs to Process Variations - An Assessment based on Analytical Solutions of 3-D Poisson's Equation," IEEE Transactions on Nanotechnology, vol. 7, no. 3, pp. 299-304, May 2008.  

75.   S.-C. Wang, Pin Su, K. Chen, C. Lin, V. Liang, G.-W. Huang, "Radio-Frequency Silicon-on-Insulator Modeling Considering the Neutral-Body Effect," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2087-2091, April 2008.  

76.   Y.-S. Wu and Pin Su, "Investigation of Random Dopant Fluctuation for Multi-Gate Metal–Oxide–Semiconductor Field-Effect Transistors Using Analytical Solutions of Three-Dimensional Poisson's Equation," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2097-2102, April 2008.  

77.   W. Lee, Pin Su, K.-W. Su, C. Chiang, S. Liu, "Investigation of Anomalous Inversion C-V Characteristics for Long-Channel MOSFETs with Leaky Dielectrics: Mechanisms and Reconstruction," IEEE Transactions on Semiconductor Manufacturing, vol. 21, no. 1, pp. 104-109, Feb. 2008.  

78.   J. Wang, W. P.-N. Chen, C. Shih, C. Lien, Pin Su, Y. Sheu, D. Chao, K. Goto, "Mobility Modeling and Its Extraction Technique for Manufacturing Strained-Si MOSFETs," IEEE Electron Device Letters, vol. 28, no. 11, pp. 1040-1043, November 2007.  

79.   Pin Su and J. J.-Y. Kuo, "On the Enhanced Impact Ionization in Uniaxial Strained p-MOSFETs," IEEE Electron Device Letters, vol. 28, no. 7, pp. 649-651, July 2007.  

80.   S.-C. Wang, Pin Su, K. Chen, C. Lin, V. Liang, G.-W. Huang, "On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs," IEEE Microwave and Wireless Components Letters, vol. 17, no. 5, pp. 364-366, May 2007.  

81.   J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Investigation of Analog Performance for Process-Induced-Strained PMOSFETs," Semiconductor Science and Technology, vol. 22, no. 4, pp. 404-407, April 2007.  

82.   W. Lee, Pin Su, K.-W. Su, C. Chiang, S. Liu, "Investigation of Inversion C-V Reconstruction for MOSFETs with Leaky Dielectrics using BSIM4/SPICE and Intrinsic Input Resistance Model," Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 1870-1873, April 2007.  

83.   W. Lee, Pin Su, H. Chen, C. Chang, K.-W. Su, S. Liu, F.-L. Yang, "An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature," IEEE Electron Device Letters, vol. 27, no. 3, pp. 182-184, March 2006.  

84.   Pin Su and W. Lee, "On the Prediction of Geometry-Dependent Floating-Body Effect in SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1662-1664, July 2005.  

85.   Pin Su and W. Lee, "Modeling Geometry-Dependent Floating-Body Effect Using Body-Source Built-In Potential Lowering for SOI Circuit Simulation," Japanese Journal of Applied Physics, vol. 44, no. 4B, pp. 2366-2370, April 2005. 

86.   M. Chan, Pin Su, H. Wan, C. Lin, S. Fung, A. Niknejad, C. Hu, P. Ko, "Modeling the Floating-Body Effects of Fully Depleted, Partially Depleted, and Body-Grounded SOI MOSFETs," Solid-State Electronics, vol. 48, pp. 969-978, June 2004.  

87.   S. Lam, H. Wan, Pin Su, P. Wyatt, A. Niknejad, C. Hu, P. Ko, M. Chan, "RF Characterization of Metal T-Gate Structure in Fully-Depleted SOI CMOS Technology," IEEE Electron Device Letters, vol. 24, no. 4, pp. 251-253, April 2003. 

88.   Pin Su, S. Fung, P. Wyatt, H. Wan, A. Niknejad, M. Chan, and C. Hu, "On the Body-Source Built-In Potential Lowering of SOI MOSFETs," IEEE Electron Device Letters, vol. 24, no. 2, pp. 90-92, February 2003. 

89.   Pin Su, K. Goto, T. Sugii, and C. Hu, "A Thermal Activation View of Low Voltage Impact Ionization in MOSFETs," IEEE Electron Device Letters, vol. 23, no. 9, pp. 550-552, September 2002. 

90.   Pin Su, K. Goto, T. Sugii, and C. Hu, "Enhanced Substrate Current in SOI MOSFETs," IEEE Electron Device Letters, vol. 23, no. 5, pp. 282-284, May 2002. 

91.   C. Kwei, C. Hung, Pin Su, and C. Tung, "Spatial Distributions of Elastically Backscattered Electrons from Copper and Silver," J. Phys. D: Appl. Phys., vol. 32, 1999. 

92.   C. Kwei, Pin Su, Y. Chen, and C. Tung, "Monte Carlo Calculations of the Reflection Electron Energy Loss Spectra in Gold," J. Phys. D: Appl. Phys., vol. 30, p. 13, 1997. 

93.   Y. Chen, C. Kwei and Pin Su, "Angular Distribution of Electrons Elastically Backscattered from Non-crystalline Solid Surfaces," J. Phys. D: Appl. Phys., vol. 28, p. 2163, 1995. 

94.   Y. Chen, C. Kwei, Pin Su, and C. Tung, "Dependence of Electron Mobility on Doped Impurties," Jpn. J. Appl. Phys., vol. 34, p. 4827, 1995. 

95.   Y. Chen, Pin Su, C. Kwei and C. Tung, "Influence of Surface Excitations on the Elastic Backscattering of Electrons from Copper and Silver Surfaces," Phys. Rev. B 50, p. 17547, 1994. 

 

(B) Conference Papers and Invited Talks

1.      Pin Su and W.-X. You, "Device Structural Effects on Negative-Capacitance FETs," 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), San Francisco, California, USA, October 2018. (Invited)

2.      W.-X. You, Pin Su and C. Hu, "Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation," 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), San Francisco, California, USA, October 2018.

3.      S.-H. Lin, S.-E. Huang, and Pin Su, "Investigation of Gate-All-Around and Double-Gate InGaAs Negative-Capacitance FETs considering Quantum Capacitance," Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2018.

4.      W.-X. You and Pin Su, "Investigation of Optimum BOX Thickness for MFIS-Type 2D Negative-Capacitance FETs," Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2018.

5.      Pin Su, "Modeling and Investigation for 2D Negative-Capacitance FETs," 2018 Taiwan-Japan Bilateral Seminar – Post Si Era Technology, Hsinchu, Taiwan, April 19th, 2018. (Invited)

6.          W.-C. Huang and Pin Su, "A New and Simple DC Method for Thermal-Resistance Extraction of Scaled FinFET Devices," 2018 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2018.

7.          H.-P. Lee, K.-Y. Tseng, and Pin Su, "Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs," 2018 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2018.

8.      P.-S. Lu, W.-X. You, and Pin Su, "Impact of Contact Resistance on 2D Negative-Capacitance FETs," 2018 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Japan, March 2018.

9.      S.-E. Huang and Pin Su, "Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs/Si Channel Negative-Capacitance FinFETs," 2018 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Japan, March 2018.

10.   W.-X. You and Pin Su, "Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors," 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), San Francisco, California, USA, October 2017.

11.   W.-C. Huang and Pin Su, "Investigation of Optimal Number of Stack for Stacked NW FETs for Logic Application," Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, September 2017.

12.   S.-E. Huang, C.-L. Yu, W.-X. You, and Pin Su, "Investigation of Quantum-induced VT Shift and Backgate-modulated VT Properties for Ultra-Thin-Body InGaAs-OI/SOI Negative-Capacitance FETs," Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, September 2017.

13.   C.-T. Zheng, Pin Su and C.-T. Chuang, "Benchmarking the Impact of Work Function Variations on Cell Stability of Low-Voltage 6T SRAMs with Non-planar and Planar TMDFETs," Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, September 2017.

14.   Pin Su, "Negative Capacitance FETs – Design Space Exploration and More," 2017 International Electron Devices and Materials Symposium (IEDMS), Hsinchu, Taiwan, September 2017. (Invited)

15.   H.-P. Lee and Pin Su, "Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs," 2017 Silicon Nanoelectronics Workshop (SNW 2017), Kyoto, Japan, June 2017.

16.   C.-N. Chang, Y.-N. Chen, P.-T. Huang, Pin Su and C.-T. Chuang, "Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, May 2017.

17.      H.-P. Lee, C.-L. Yu, W.-X. You, and Pin Su, "Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs," 2017 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2017.

18.   C.-H. Yu, J.-T. Zheng, Pin Su and C.-T. Chuang, "Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node," 2017 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2017.

19.      H.-Y. Lee, C.-H. Yu, Pin Su and C.-T. Chuang, "Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETs," 2017 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2017.

20.   M.-H. Tu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Exploration and Evaluation of TCAM with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications," 2017 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2017.

21.   J.-H. Wang, Pin Su and C.-T. Chuang, "Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs," 2017 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2017.

22.   W.-X. You and Pin Su, "Design Space Exploration Considering Back-Gate Biasing Effects for Negative-Capacitance Transition-Metal-Dichalcogenide (TMD) Field-Effect Transistors," 2017 1st Electron Devices Technology and Manufacturing Conference (EDTM), Toyama, Japan, March 2017.

23.   C.-H. Yu, Pin Su and C.-T. Chuang, "Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold Applications," 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), San Francisco, California, USA, October 2016.

24.      W.-X. You and Pin Su, "A New Scale-Length Model for Short-Channel Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) Field-Effect Transistors," Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2016.

25.   C.-H. Yu, Pin Su and C.-T. Chuang, "Impacts of Device Design and Variability on 6T/8T SRAM Cells with MoS2-n/WSe2-p MOSFETs for 5.9nm node," Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2016.

26.      C.-P. Tsai and Pin Su, "New Findings on the Gate-Length Dependence of Subthreshold Swing for Ultra-Thin-Body Negative Capacitance FETs," Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2016.

27.   C.-L. Yu, C.-H. Yu, and Pin Su, "Theoretical Investigation and Benchmarking of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs," Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2016.

28.   C.-H. Yu, Pin Su and C.-T. Chuang, "Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells," International Symposium on Low Power Electronics and Design (ISLPED 2016), San Francisco, California, USA, August 2016.

29.   J.-H. Wang, Y.-N. Chen, Pin Su and C.-T. Chuang, "Exploration and Evaluation of Hybrid TFET-MOSFET Monolithic 3D SRAMs Considering Interlayer Coupling," 2016 IEEE International Conference on IC Design and Technology (ICICDT), Ho Chi Minh City, Vietnam, June 2016.

30.   S.-H. Wu and Pin Su, "Investigation of Intrinsic Drain-Induced Barrier Lowering Characteristics for Scaled Tri-Gate n-MOSFETs with InGaAs Channel," 5rd International Symposium on Next-Generation Electronics (ISNE), Hsinchu, Taiwan, May 2016.

31.   V. P.-H. Hu, Pin Su and C.-T. Chuang, "Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-Thin-Body GeOI MOSFETs," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016.

32.   V. P.-H. Hu, C.-T. Lo, A. B. Sachid, Pin Su and C. Hu, "Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap," 2016 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2016.

33.   C.-H. Yu, Pin Su and C.-T. Chuang, "Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits," 2016 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2016.

34.   C.-T. Lo, V. P.-H. Hu, and Pin Su, "Higher-k Gate-Dielectric induced Degradation in Electrostatic Integrity and Mitigation by Spacer Design for Multi-Gate InGaAs-OI FinFETs," 2015 International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, November 2015.

35.      S.-L. Shen, H.-H. Shen, C.-H. Yu, and Pin Su, "Investigation and Comparison of Quantum-Capacitance Induced Inversion-Charge Loss for Ultra-Thin-Body and Double-Gate III-V n-MOSFETs," Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, September 2015.

36.   Y.-N. Chen, Pin Su, J. C.-S. Woo and C.-T. Chuang, "Investigation of FOM of Tunnel FET Devices and OTA Design for Analog/Mixed-Signal Applications," Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, September 2015.

37.   Y.-W. Wang and Pin Su, "Optimized Nanowire Diameter for III-V Homojunction and Heterojunction Gate-All-Around Tunnel FETs," Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, September 2015.

38.      S.-E. Huang, M.-L. Fan, and Pin Su, "Investigation of Backgating Effect on Superlinear Onset of Output Characteristics for UTB III-V Heterojunction Tunnel FET," Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, September 2015.

39.      K.-C. Yu, C.-H. Yu, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Impacts of Threshold Voltage Design for Monolithic 3D 6T SRAM with Si and InGaAs-n/Ge-p Devices considering Interlayer Coupling," Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, September 2015.

40.      T.-C. Wu, C.-J. Chen, Y.-N. Chen, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications," 28th IEEE International System-On-Chip Conference (SOCC 2015), Beijing, China, September 2015.

41.   C.-H. Yu and Pin Su, "Investigation and Benchmark of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs," 15th International IEEE Conference on Nanotechnology (IEEE NANO 2015), Rome, Italy, July 2015.

42.   V. P.-H. Hu, Pin Su and C.-T. Chuang, "UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability," 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2015), Hsinchu, Taiwan, June 29 - July 2, 2015 (Best Paper Award).

43.   C.-H. Yu and Pin Su, "Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its Suppression," 2015 Silicon Nanoelectronics Workshop (SNW 2015), Kyoto, Japan, June 2015.

44.   T.-C. Wu, C.-J. Chen, Y.-N. Chen, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices," 2015 IEEE International Conference on IC Design and Technology (ICICDT), Leuven, Belgium, June 2015.

45.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015.

46.   C.-J. Chen, Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015.

47.   H.-H. Shen, C.-H. Yu, and Pin Su, "Investigation of Quantum-Capacitance induced Drain-Current Loss for Multi-gate InGaAs n-MOSFETs," 2015 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2015.

48.   K.-C. Yu, M.-L. Fan, Pin Su and C.-T. Chuang, "Analysis of Monolithic 3D 6T SRAM using Ultra-Thin-Body InGaAs/Ge MOSFETs considering Interlayer Coupling," 2015 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2015.

49.   V. P.-H. Hu, A. B. Sachid, C.-T. Lo, Pin Su and C. Hu, "Electrostatic Integrity and Performance Enhancement for UTB InGaAs-OI MOSFET with High-k Dielectric through Spacer Design," 2015 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2015.

50.      V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Stability Analysis for UTB GeOI 6T SRAM Cells considering NBTI and PBTI," 2015 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2015.

51.      Pin Su, "New Findings on III-V-on-Insulator Devices enabled by TCAD," Workshop on Simulation of Semiconductor Processes and Devices, Hsinchu, Taiwan, November 2014. (Invited)

52.   H.-H. Shen, C.-H. Yu, and Pin Su, "Impact of Quantum Capacitance on Intrinsic Inversion Capacitance for Tri-gate InGaAs-on-Insulator n-MOSFETs," 2014 International Electron Devices and Materials Symposium (IEDMS), Hualien, Taiwan, November 2014.

53.      S.-H. Wu, C.-H. Yu, and Pin Su, "Enhanced Multi-VTH Modulation Efficiency in Tri-gate GeOI p-MOSFETs," 2014 International Electron Devices and Materials Symposium (IEDMS), Hualien, Taiwan, November 2014.

54.      K.-C. Yu, M.-L. Fan, Pin Su and C.-T. Chuang, "Leakage-Delay Analysis of Monolithic 3D Logic Circuits using Ultra-Thin-Body InGaAs/Ge MOSFETs considering Interlayer Electrical Coupling," Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2014.

55.      C.-W. Hsu, M.-L. Fan, and Pin Su, "Investigation and Mitigation of Work-Function Variation for III-V Heterojunction Tunnel FET," Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2014.

56.      C.-J. Chen, Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Impacts of Work Function Variation and Line-Edge Roughness of TFET and FinFET Devices and Logic Circuits," 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Millbrae, California, October 2014.

57.   C.-H. Yu and Pin Su, "Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET," 2014 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, USA, June 2014.

58.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling," Proceedings of 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 2014 (Finalist for the ISCAS 2014 Student Best Paper Award).

59.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Evaluation of Read- and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells," Proceedings of 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 2014.

60.   K.-C. Lee, M.-L. Fan, and Pin Su, "Comparison of Analog FOM for TFET and FinFET Considering Line-Edge Roughness," 3rd International Symposium on Next-Generation Electronics (ISNE), Taoyuan, Taiwan, May 2014.

61.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Stability/Performance Assessment of Monolithic 3D 6T/8T SRAM Cells Considering Transistor-Level Interlayer Coupling," Proceedings of 2014 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2014.

62.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Comprehensive Analysis of Ultra-Thin-Body MOSFETs for Monolithic 3D Logic Circuits with Interlayer Coupling," Proceedings of 2013 International Semiconductor Device Research Symposium (ISDRS), Maryland, USA, December 2013.

63.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM Cells," Proceedings of the 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), Monterey, California, October 2013.

64.      K.-C. Lee, M.-L. Fan, and Pin Su, "Comparison of Analog FOM for TFET and FinFET Considering Work Function Variation," Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 2013.

65.      C.-W. Yang and Pin Su, "Investigation of Random Grain-Boundary Induced Variability for Stackable NAND Flash Using 3D Voronoi Grain Patterns," Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 2013.

66.      V. P.-H. Hu, H.-H. Shen, M.-L. Fan, Pin Su and C.-T. Chuang, "Leakage-Delay Analysis of InxGa1-xAs-OI FinFETs for Logic Applications," Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 2013.

67.   S.-H. Wu, Y.-S. Wu, and Pin Su, "Investigation of Temperature Dependence of DIBL for InGaAs Multi-Gate n-MOSFETs Considering Quantum Confinement," Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 2013.

68.      Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Investigation of Tunneling FET Device Designs for Improving Circuit Switching Performance and Energy," Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 2013.

69.      C.-H. Yu and Pin Su, "Investigation of Backgate-Bias Dependence of Intrinsic Variability for UTB Hetero-Channel MOSFETs Considering Quantum Confinement," Proceedings of the 71st Annual Device Research Conference (DRC), Notre Dame, IN, USA, June 2013.

70.   S.-H. Wu, Y.-S. Wu, and Pin Su, "Investigation of 2-D Quantum Confinement Effect on DIBL for Multi-Gate n-MOSFETs with InGaAs Channel," Proceedings of the 2013 Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2013.

71.      C.-H. Yu and Pin Su, "Impact of Quantum Confinement on the Benchmark of Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body MOSFETs with Various High-Mobility Channel Materials," Abstracts of the European Materials Research Society (E-MRS) 2013 Spring Meeting (Symposium I - The route to post-Si CMOS devices: from high mobility channels to graphene-like 2D nanosheets), Strasbourg, France, May 2013.

72.   S.-Y. Yang, Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits," Proceedings of the 2013 IEEE International Conference on IC Design and Technology (ICICDT), Pavia, Italy, May 2013.

73.   J. J.-Y. Kuo, M.-L. Fan, W. Lee, and Pin Su, "Source/Drain Series Resistance Induced Feedback Effect on Drain Current Mismatch and Its Implication," Proceedings of the IEEE 2013 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2013.

74.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices," Proceedings of the IEEE 2013 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2013.

75.   M.-F. Tsai, M.-L. Fan, C.-H. Pao, Y.-N. Chen, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs," Proceedings of the IEEE 2013 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2013.

76.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers," Proceedings of the 2013 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, April 2013.

77.      V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates," Proceedings of the 2013 International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, March 2013.

78.   M.-F. Tsai, J.-H. Tsai, M.-L. Fan, Pin Su and C.-T. Chuang, "Variation Tolerant CLSAs for Nanoscale Bulk CMOS and FinFET SRAM," 2012 Asia Pacific Conference on Circuits and Systems (APCCAS), Kaohsiung, Taiwan, December 2012.

79.   C.-H. Pao, M.-L. Fan, M.-F. Tsai, Y.-N. Chen, V. P.-H. Hu, Pin Su and C.-T. Chuang, "A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits," 2012 Asia Pacific Conference on Circuits and Systems (APCCAS), Kaohsiung, Taiwan, December 2012.

80.   C.-W. Yang, S.-H. Chao, and Pin Su, "Simulation of Grain-Boundary Induced Vth Variability in Stackable NAND Flash Using a Voronoi Approach," 12th Non-Volatile Memory Technology Symposium (NVMTS 2012), Singapore, November 2012.

81.      C.-H. Yu and Pin Su, "Impact of Backgate Bias on the Sensitivity of Threshold Voltage to Process and Temperature Variations for Ultra-Thin-Body GeOI and InGaAs-OI MOSFETs Considering Quantum Confinement," Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, Japan, September 2012.

82.   S.-H. Chao, M.-L. Fan, and Pin Su, "Investigation and Comparison of Work Function Variation for FinFET and Ultra-Thin-Body SOI Devices Using a Voronoi Approach," Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, Japan, September 2012.

83.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, K.-C. Lee, Pin Su and C.-T. Chuang, "Variability Analysis of Sense Amplifier for Subthreshold Ultra-Thin-Body SOI SRAM Applications," Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, Japan, September 2012.

84.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Stability and Performance Optimization of InGaAs-OI and GeOI Heterochannel SRAM Cells," Proceedings of the 42th European Solid-State Device Research Conference (ESSDERC 2012), Bordeaux, France, September 2012.

85.   Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, M.-F. Tsai, C.-H. Pao, Pin Su and C.-T. Chuang, "A Comparative Analysis of Tunneling FET Circuit Switching Characteristics and SRAM Stability and Performance," Proceedings of the 42th European Solid-State Device Research Conference (ESSDERC 2012), Bordeaux, France, September 2012.

86.      C.-H. Pao, M.-L. Fan, M.-F. Tsai, Y.-N. Chen, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Impacts of Random Telegraph Noise on the Analog Properties of FinFET and Trigate Devices and Widlar Current Source," Proceedings of the 2012 IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, USA, May 2012.

87.      Pin Su, "Some Aspects of High-Mobility Channel CMOS Devices," Abstract Digest of the 2012 Symposium on Nano Device Technology (SNDT 2012), Hsinchu, Taiwan, April 2012, S1-3, p. 11. (Invited)

88.      Y.-S. Wu, C.-H. Chiang, and Pin Su, "Investigation of Scalability for Ge and InGaAs Channel Multi-Gate NMOSFETs," Proceedings of the IEEE 2012 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2012.

89.      C.-H. Chiang, M.-L. Fan, J. J.-Y. Kuo, and Pin Su, "Body Effect Induced Variability in Bulk Tri-gate MOSFETs," Proceedings of the IEEE 2012 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2012.

90.      M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Comparison of Differential and Large-Signal Sensing Scheme for Subthreshold/Superthreshold FinFET SRAM Considering Variability," Proceedings of the IEEE 2012 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2012.

91.      M.-F. Tsai, B. K.-Y. Lu, M.-L. Fan, C.-H. Pao, Y.-N. Chen, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Impacts of Wire-LER on Nanowire MOSFET Devices, Subthreshold SRAM and Logic Circuits," Proceedings of the IEEE 2012 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2012.

92.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits," Proceedings of the 2012 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, USA, April 2012.

93.   J. J.-Y. Kuo and Pin Su, "Self-Heating Induced Feedback Effect on Drain Current Mismatch and Its Modeling," 2011 International Electron Devices Meeting (IEDM), Washington DC, USA, December 2011.

94.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Comprehensive Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells considering Variability and Temperature Sensitivity," 2011 International Electron Devices Meeting (IEDM), Washington DC, USA, December 2011.

95.   M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, Pin Su and C.-T. Chuang, "Impact of Single Trap Induced Random Telegraph Noise on FinFET Device and SRAM Stability," Proceedings of the 2011 IEEE International SOI Conference, October 2011.

96.   J. J.-Y. Kuo and Pin Su, "Investigation of Subthreshold Drain Curreut Mismatch Characteristics for Nanoscale MOSFETs," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, September 2011.

97.   C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and Pin Su, "Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage Characteristics for Ultra-Thin-Body Germanium-On-Insulator MOSFETs," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, September 2011.

98.   B. K.-Y. Lu, M.-L. Fan, and Pin Su, "Impact of Aspect Ratio on the Subthreshold RTN Amplitude of Multi-Gate MOSFETs," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, September 2011.

99.   V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Analysis of Power-Performance for Ultra-Thin-Body GeOI Logic Circuits," International Symposium on Low Power Electronics and Design (ISLPED 2011), Fukuoka, Japan, August 2011.

100.C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and Pin Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs considering Quantum Confinement," Proceedings of the 2011 IEEE International NanoElectronics Conference (INEC), Tao-Yuan, Taiwan, June 2011.

101.Y.-S. Wu and Pin Su, "Detailed Study of “Dark Space” and Electrostatic Integrity for Ge MOSFETs with High-k Dielectric Using Analytic Solution of Schrodinger Equation," Proceedings of the 2011 Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2011.

102.  V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Variability Analysis of UTB SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation and Temperature Sensitivity," Proceedings of the 2011 IEEE International Conference on IC Design and Technology (ICICDT), Kaohsiung, Taiwan, May 2011 (Best Student Paper Award).

103.  J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Temperature Dependence of Device Mismatch and Harmonic Distortion in Nanoscale Uniaxial-Strained PMOSFETs," Proceedings of the 2011 IEEE International Conference on IC Design and Technology (ICICDT), Kaohsiung, Taiwan, May 2011.

104.Y.-N. Chen, C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Impacts of Intrinsic Device Variations on the Stability of FinFET Subthreshold SRAMs," Proceedings of the 2011 IEEE International Conference on IC Design and Technology (ICICDT), Kaohsiung, Taiwan, May 2011.

105.Y.-S. Wu, H.-Y. Hsieh, V. P.-H. Hu, and Pin Su, "Beneficial Effects of Quantum Confinement on Ge and InGaAs Ultra-Thin-Body NMOS Devices," Proceedings of the IEEE 2011 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2011.

106.V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Leakage-Delay Analysis of Ultra-Thin-Body GeOI Devices and Logic Circuits," Proceedings of the IEEE 2011 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2011.

107.Y.-N. Chen, C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Disturb-Free Independently-Controlled-Gate 7T FinFET SRAM Cell," Proceedings of the IEEE 2011 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2011.

108.V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, “Evaluation of Static Noise Margin and Performance of 6T FinFET SRAM Cells with Asymmetric Gate to Source/Drain Underlap Devices,” Proceedings of the 2010 IEEE International SOI Conference, San Diego, California, USA, October 2010.

109.C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs,” Proceedings of the 2010 IEEE International SOI Conference, San Diego, California, USA, October 2010.

110.W. P.-N. Chen, J. J.-Y. Kuo, B. K.-Y. Lu, and Pin Su, "Experimental Investigation and Modeling for Surface Roughness Limited Mobility in Strained pMOSFETs," Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2010.

111.V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, Pin Su and C.-T. Chuang, "High-k Metal Gate FinFET SRAM Cell Optimization Considering Variability due to NBTI/PBTI and Surface Orientation," Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2010.

112.B. K.-Y. Lu and Pin Su, "Impact of Quantum Mechanical Effects on Silicon Nanowire Biosensors," Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2010.

113.M.-L. Fan, V. P.-H. Hu, C.-Y. Hsieh, Pin Su and C.-T. Chuang, "Subthreshold FinFET SRAM Cell Optimization Considering Surface-Orientation Dependent Variability," Proceedings of the 40th European Solid-State Device Research Conference (ESSDERC), Seville, Spain, September 2010, pp. 198-201.

114.V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, Pin Su and C.-T. Chuang, "FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI and Surface Orientation," Proceedings of the 15th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Bologna, Italy, September 2010, pp. 269-272.

115.Y.-S. Wu, M.-L. Fan, and Pin Su, "Impact of Surface Orientation on Vth Variability of FinFET," Proceedings of the 2010 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, USA, June 2010, pp. 75-76.

116.Pin Su, "Variability in Nano-CMOS," Abstract Digest of the 2010 Symposium on Nano Device Technology (SNDT 2010), Hsinchu, Taiwan, May 2010, S3-4, p. 20. (Invited)

117.M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Investigation of Stability and AC Performance of Sub-threshold FinFET SRAM," Proceedings of the IEEE 2010 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2010, pp. 66-67.

118.V. P.-H. Hu, Y.-S. Wu, and Pin Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body GeON MOSFET," Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, October 2009.

119.V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Subthreshold SRAM with Enhanced Stability using Ultra-Thin-Body and BOX SOI," Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, October 2009.

120.Y.-S. Wu and Pin Su, "Quantum Confinement Effect in Short-Channel Gate-All-Around MOSFETs and Its Impact on the Sensitivity of Threshold Voltage to Process Variations," Proceedings of the 2009 IEEE International SOI Conference, Foster City, California, USA, October 2009.

121.M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, Pin Su and C.-T. Chuang, "Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region," Proceedings of the 2009 IEEE International SOI Conference, Foster City, California, USA, October 2009.

122.J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "New Findings on Low Frequency Noise and Mismatching Properties in Uniaxial Strained PMOSFETs," Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC), Athens, Greece, September 2009, pp. 327-330.

123.V. P.-H. Hu, M.-L. Fan, Pin Su and C.-T. Chuang, "Impact of Work Function Design on the Stability and Performance of Ultra-Thin-Body SOI Subthreshold SRAM," Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC 2009), Athens, Greece, September 2009, pp. 145-148.

124.S.-C. Wang, Pin Su, K. Chen, S. Huang, C. Hung, G.-W. Huang, "Temperature Dependences of RF Small-Signal Characteristics for the SOI Dynamic Threshold Voltage MOSFET," European Microwave Integrated Circuits Conference (EuMIC 2009), Rome, Italy, September 2009.

125.V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, Pin Su and C.-T. Chuang, "Design and Analysis of Ultra-Thin-Body SOI Based Subthreshold SRAM," International Symposium on Low Power Electronics and Design (ISLPED 2009), San Francisco, California, USA, August 2009, pp. 9-14.

126.W. Lee, J. J.-Y. Kuo, W. P.-N. Chen, Pin Su and M. Jeng, "Impact of Uniaxial Strain on Channel Backscattering Characteristics and Drain Current Variation for Nanoscale PMOSFETs," 2009 Symposium on VLSI Technology, Kyoto, Japan, June 2009, pp. 112-113.

127.Y.-S. Wu, M.-L. Fan, and Pin Su, "Investigation of Switching Time Variations for FinFET and Bulk MOSFETs Using the Effective Drive Current Approach," Proceedings of the 2009 Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2009, pp. 7-8.

128.J. J.-Y. Kuo, M.-L. Fan, and Pin Su, "Investigation of Mismatching Properties in Nanoscale MOSFETs with Symmetric/Asymmetric Halo Implant," Proceedings of the 2009 Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2009, pp. 127-128.

129.J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Investigation of Low Frequency Noise in Uniaxial Strained PMOSFETs," Proceedings of the IEEE 2009 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2009, pp. 82-83.

130.V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, Pin Su and C.-T. Chuang, "Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in Subthreshold Region using Analytical Solution of Poisson's Equation," Proceedings of the IEEE 2009 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2009, pp. 115-116.

131.V. P.-H. Hu, Y.-S. Wu, and Pin Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body GeOI MOSFET Using Analytical Solution of Poisson’s Equation," Proceedings of the 2008 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2008), Hong Kong, December 2008.

132.W. Lee and Pin Su, "Investigation of Channel Backscattering Characteristics for Nanoscale SOI MOSFETs Using a New Temperature-Dependent Method," Proceedings of the 2008 IEEE International SOI Conference, New York, USA, October 2008, pp. 73-74.

133.W. P.-N. Chen, Pin Su, K. Goto, "A Comprehensive Study of Coulomb Scattering Mobility in Short-Channel Process-Induced Strain NMOSFETs," Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2008, pp. 708-709.

134.Y.-S. Wu and Pin Su, "Subthreshold Current Model of Cylindrical Gate-All-Around Nanowire MOSFETs Using Analytical Solutions of Poisson's Equation," Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2008, pp. 450-451.

135.S.-C. Wang, Pin Su, K. Chen, C. Lin, V. Liang, G.-W. Huang, "RF Small-Signal and Noise Modeling for SOI Dynamic Threshold Voltage MOSFETs," Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2008, pp. 414-415.

136.W. Lee and Pin Su, "A Comprehensive Study of Single-Electron Effects in Multiple-Gate MOSFETs," Proceedings of the 2008 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, USA, June 2008.

137.J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Investigation of Matching Performance for Uniaxial Strained PMOSFETs," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2007, p. 82.

138.Y.-S. Wu and Pin Su, "Investigation of Random Dopant Fluctuation for Multi-Gate MOSFETs Using Analytical Solution of 3-D Poisson's Equation," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2007, p. 440.

139.W. P.-N. Chen, Pin Su, T. Wang, J. Wang, C. Lien, S. Cheng, K. Goto, S. Yang, C. Diaz, "Investigation of Coulomb Mobility in Nanoscale Strained PMOSFET," Proceedings of the 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2007, p. 15.

140.Y.-S. Wu and Pin Su, "Investigation of Variability for Multi-Gate MOSFETs Using Analytical Solution of 3-D Poisson’s Equation," Proceedings of the 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2007, p. 87.

141.W. Lee, Pin Su, H. Chen, C. Chang, K. Su, S. Liu, F.-L. Yang, "An Experimental Assessment of Quantum Interference in Multiple-Gate SOI nMOSFETs with Non-Overlapped Gate to Source/Drain Structure near Room Temperature," Proceedings of the 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2007, p. 27.

142.Y.-S. Wu and Pin Su, "Investigation of Scaling for Multi-Gate Transistors Using Analytical Solution of 3-D Poisson’s Equation," Proceedings of the IEEE 2007 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2007, p. 160.

143.J. Wang, W. P.-N. Chen, C. Shih, C. Lien, Pin Su, Y. Sheu, D. Chao, K. Goto, "Accurate Modeling and Characterization of Mobility in Tensile and Compressive Stress for State-of-the-Art Manufacturing NMOSFETs," Proceedings of the IEEE 2007 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2007, p. 158.

144.W. Lee, Pin Su, H. Chen, C. Chang, K. Su, S. Liu, F.-L. Yang, "Controlled Single-Electron Effects in Multiple-Gate SOI MOSFETs near Room Temperature," Proceedings of the 2006 IEEE International SOI Conference, New York, USA, October 2006, p. 63.

145.J. J.-Y. Kuo, W. P.-N. Chen, and Pin Su, "Investigation of Analog Performance for Uniaxial Strained PMOSFETs," Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 2006, p. 610.

146.W. Lee, Pin Su, K.-W. Su, C. Chiang, S. Liu, "Investigation of Inversion C-V Reconstruction for Long-Channel MOSFETs with Leaky Dielectrics using Intrinsic Input Resistance Approach," Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 2006, p. 416.

147.S.-C. Wang, Pin Su, K. Chen, C. Lin, V. Liang, G.-W. Huang, "RF Extrinsic Resistance Extraction Considering Neutral-Body Effect for Partially-Depleted SOI MOSFETs," Proceedings of the IEEE 2006 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2006, p. 139.

148.W. P.-N. Chen, Pin Su, J. Wang, C. Lien, C. Chang, K. Goto, C. Diaz, "A New Series Resistance and Mobility Extraction Method by BSIM Model for Nano-Scale MOSFETs," Proceedings of the IEEE 2006 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2006, p. 143.

149.W. Lee, Pin Su, H. Chen, C. Chang, K. Su, S. Liu, F.-L. Yang, "An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature," Proceedings of 2005 International Semiconductor Device Research Symposium (ISDRS), Washington D.C., USA, December 2005.

150.H. Wan, Pin Su, S. Fung, C. Chen, P. Wyatt, A. Niknejad, and C. Hu, "RF Modeling for FDSOI MOSFET and Self Heating Effect on RF Parameter Extraction," Technical Proceedings of the 2005 International Conference on Modeling and Simulation of Microsystems (MSM), Anaheim, CA, USA, May 2005.

151.  W. Lee, K. Su, C. Chiang, S. Liu, and Pin Su, "Inversion MOS Capacitance Extraction for Ultra-Thin Gate Oxide using BSIM4," Proceedings of the IEEE 2005 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2005, pp. 62-63.

152.  Pin Su and W. Lee, "Modeling Geometry-Dependent Floating-Body Effect using Body-Source Built-In Potential Lowering for Scaled SOI CMOS," Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2004, pp. 510-511.

153.C. Lin, Pin Su, Y. Taur, X. Xi, J. He, A. Niknejad, M. Chan, and C. Hu, "Circuit Performance of Double-Gate SOI CMOS," Proceedings of 2003 International Semiconductor Device Research Symposium (ISDRS), Washington D.C., USA, December 2003.

154.Pin Su, S. Fung, P. Wyatt, H. Wan, M. Chan, A. Niknejad, and C. Hu, "A Unified Model for Partial-Depletion and Full-Depletion SOI Circuit Designs: Using BSIMPD as a Foundation," Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, San Jose, CA, USA, September 2003, pp. 241-244.

155.A. Niknejad, M. Chan, C. Hu, B. Brodersen, X. Xi, J. He, Y. Cao, S. Emami-Neyestanak, C. Doan, Pin Su, H. Wan, M. Dunga, C. Lin, "Compact Modeling for RF and Microwave Integrated Circuits," Technical Proceedings of the 2003 International Conference on Modeling and Simulation of Microsystems (MSM), pp. 294-297, February 2003.

156.Pin Su, S. Fung, H. Wan, A. Niknejad, M. Chan, and C. Hu, "An Impact Ionization Model for SOI Circuit Simulation," Proceedings of the 2002 IEEE International SOI Conference, Williamsburg, VA, USA, Oct. 2002, pp. 201-202.

157.H. Wan, S. Fung, Pin Su, M. Chan, and C. Hu, "Tendency for Full Depletion Due to Gate Tunneling Current," Proceedings of the 2002 IEEE International SOI Conference, Williamsburg, VA, USA, Oct. 2002, pp. 140-141.

158.S. Fung, Pin Su, and C. Hu, "Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application," Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems (MSM), pp. 690-693, April 2002.

159.Pin Su, K. Goto, T. Sugii, and C. Hu, "Excess Hot-Carrier Currents in SOI MOSFETs and Its Implications," Proceedings of the 2002 IEEE International Reliability Physics Symposium, Dallas, TX, USA, April 2002, pp. 93-97.

160.Pin Su, S. Fung, W. Liu, and C. Hu, "Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD," Proceedings of the 2002 International Symposium on Quality Electronic Design, San Jose, CA, USA, March 2002, pp. 487-491.

161.Pin Su, K. Goto, T. Sugii, and C. Hu, "Self-Heating Enhanced Impact Ionization in SOI MOSFETs," Proceedings of the 2001 IEEE International SOI Conference, Durango, CO, USA, Oct. 2001, pp. 31-32.

162.K. Goto, Pin Su, Y. Tagawa, T. Sugii and C. Hu, "80nm SOI CMOS Parameter Extraction for BSIMPD," Proceedings of the 2001 IEEE International SOI Conference, Durango, CO, USA, Oct. 2001, pp. 55-56.

163.H. Nakayama, Pin Su, C. Hu, M. Nakamura, H. Komatsu, K. Takeshita, and Y. Komatsu, "Methodology of Self-Heating Free Parameter Extraction and Circuit Simulation for SOI CMOS," Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, San Diego, CA, USA, May 2001, pp. 381-384.

164.K. Cao, W. Lee, W. Liu, X. Jin, Pin Su, S. Fung, J. An, B. Yu, and C. Hu, "BSIM4 Gate Leakage Model Including Source-Drain Partition," Technical Digest IEDM 2000, pp. 815-818, December 2000.

165.Pin Su, S. Fung, S. Tang, F. Assaderaghi, and C. Hu, "BSIMPD: A Partial-Depletion SOI MOSFET Model for Deep-Submicron CMOS Designs," Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, Orlando, FL, USA, May 2000, pp. 197-200.

166.Pin Su, S. Fung, F. Assaderaghi, and C. Hu, "A Body-Contact SOI MOSFET Model for Circuit Simulation," Proceedings of the 1999 IEEE International SOI Conference, Rohnert Park, CA, USA, Oct. 1999, pp. 50-51.

167.D. Sinitsky, S. Fung, S. Tang, Pin Su, M. Chan, P. Ko, and C. Hu, "A Dynamic Depletion SOI MOSFET Model for SPICE," Technical Digest of 1998 Symposium on VLSI Technology, p. 114, June 1998.

 

(C) Other Important Publication

1.      Pin Su, "An International Standard Model for SOI Circuit Design," Ph.D. dissertation, Department of EECS, University of California at Berkeley, Memorandum No. UCB/ERL M02/40, December 2002 (Advisor: Chenming Hu).