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       Last update: 2016/09/17

   Journal Publication  [Return to Top]

  1. M.-J. Yu, R.-P. Lin, Y.-H. Chang, and T.-H. Hou, "High-voltage amorphous InGaZnO TFT with Al2O3 high-k dielectric for low-temperature monolithic 3-D integration," accepted by IEEE Trans. Elec. Dev. 

  2. F.-J. Hou, P.-J. Sung, F.-K. Hsueh, C.-T. Wu, Y.-J. Lee, Y. Li, S. Samukawa, and T.-H. Hou, "Suspended diamond-shaped nanowire with four {111} facets for high-performance Ge gate-all-around FETs," accepted by IEEE Trans. Elec. Dev. 

  3. I-T. Wang, C.-C. Chang, L.-W. Chiu, T. Chou, and T.-H. Hou, "3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications," Nanotechnology, vol. 27, 365204, Aug. 2016.  [LINK[PDF]

  4. J.-H. Huang, H.-H. Chen, P.-S. Liu, L.-S. Lu, C.-T. Wu, C.-T. Chou, Y.-J. Lee, L.-J. Li, W.-H. Chang, and T.-H. Hou, "Large-area few-layer MoS2 deposited by sputtering," Material Research Express, vol. 3, 065007, June 2016.  [LINK[PDF]

  5. B. Hudec, C.-W. Hsu, I-T. Wang, W.-L. Lai, C.-C. Zhang, T. Wang, K. Frohlich, C.-H. Ho, C.-H. Lin, and T.-H. Hou, "3D resistive RAM cell design for high-density storage class memory - a review," Sci China Inf Sci, vol. 59, no. 6, 061403, June 2016.  [LINK[PDF]

  6. F.-J. Hou, P.-J. Sung, F.-K. Hsueh, C.-T. Wu, Y.-J. Lee, M.-N. Chang, Y. Li, and T.-H. Hou, "32-nm multigate Si-nTFET with microwave-annealed abrupt junction," IEEE Trans. Elec. Dev., vol. 63, no. 5, pp. 1808-1813, May 2016.  [LINK[PDF]

  7. B. Hudec, I-T. Wang, W.-L. Lai, C.-C. Chang, P. Jančovič, K. Frohlich, M. Mičušík, M. Omastova, and T.-H. Hou, "Interface engineered HfO2-based 3D vertical ReRAM," J. Physics D: Appl. Phys., vol. 49, 215102, Apr. 2016.  [LINK[PDF]

  8. L.-J. Chi, M.-J. Yu, Y.-H. Chang, and T.-H. Hou, "1-V full-swing depletion-load a-In–Ga–Zn–O inverters for back-end-of-line compatible 3D integration," IEEE Electron Device Letters, vol. 37, no. 4, pp. 441-444, Apr. 2016.  [LINK[PDF]

  9. Y.-H. Chang, M.-J. Yu, R.-P. Lin, C.-P. Hsu, and T.-H. Hou, "Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric," Appl. Phys. Lett., vol. 108, 033502, Jan. 2016.  [LINK[PDF]

  10. C.-T. Chou, B. Hudec, C.-W. Hsu, W.-L. Lai, C.-C. Chang, and T. H. Hou, "Crossbar array of selector-less TaOx/TiO2 bilayer RRAM," Microelectronics Reliability, vol. 55, no. 11, pp. 2220–2223, Nov. 2015.  [LINK[PDF]

  11. W.-T. Hsu, Y.-L. Chen, C.-H. Chen, P.-S. Liu, T.-H. Hou, L.-J. Li, and W.-H. Chang, "Optically initialized robust valley-polarized holes in monolayer WSe2," Nature Communication, vol. 6, 8963, Oct. 2015.  [LINK[PDF]

  12.  L. Gao, I.-T. Wang, P.-Y. Chen, S. Vrudhula, J.-S. Seo, Y. Cao, T.-H. Hou, and S. Yu, "Fully parallel write/read in resistive synaptic array for accelerating on-chip learning," Nanotechnology, vol. 26, 455204, Oct. 2015.  [LINK[PDF]

  13.  J.-C. Liu, C.-W. Hsu, I.-T. Wang, and T.-H. Hou, "Categorization of multilevel-cell storage-class memory: an RRAM example," IEEE Trans. Elec. Dev., vol. 62, no. 8, pp. 2510-2516, Aug. 2015.  [LINK[PDF]

  14. Y.-F. Wang, Y.-C. Lin, I.-T. Wang, T.-P. Lin, and T. H. Hou, "Characterization and modeling of nonfilamentary Ta/TaOx/TiO2/Ti analog synaptic device," Scientific Reports, vol. 5, 10150, May 2015.  [LINK[PDF] 

  15. L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T. H. Hou, H.-S. Philip Wong, and Y. Nishi, "Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations," Nanoscale, vol. 6, pp. 5698-5702, Jun. 2014.  [LINK[PDF] 

  16.  C. W. Hsu, Y. F. Wang, C. C. Wan, I. T. Wang, C. T. Chou, W. L. Lai, Y. J. Lee, and T. H. Hou, "Homogeneous barrier modulation of TaOx/TiO2 bilayer for ultra-high endurance three-dimensional storage-class memory," Nanotechnology, no. 25, 165202, Mar. 2014. [LINK[PDF] 

  17. W. C. Luo, J. C. Liu, Y. C. Lin, C. L. Lo, J. J. Huang, K. L. Lin, and T. H. Hou, "Statistical model and rapid prediction of RRAM SET speed–disturb dilemma," IEEE Trans. Elec. Dev., vol. 60, no. 11, pp. 3760-3766, Nov. 2013. [LINK[PDF] 

  18. S. C. Wu, H. T. Feng, M. J. Yu, I. T. Wang, and T. H. Hou, “Flexible three-bit-per-cell resistive-switching memory using a-IGZO TFTs,” IEEE Electron Device Letters, vol. 34, no. 10, pp. 1265-1267, Oct. 2013. [LINK[PDF] 

  19. W. C. Luo, T. H. Hou, K. L. Lin, Y. J. Lee, and T. F. Lei, "Reversible transition of resistive switching induced by oxygen-vacancy and metal filaments in HfO2," Solid-State Electron., vol. 89, pp. 167–170, Aug. 2013. [LINK[PDF] 

  20. C. W. Hsu, T. H. Hou, M. C. Chen, I. T. Wang, and C. L. Lo, “Bipolar Ni/TiO2/HfO2/Ni RRAM with multilevel states and self-rectifying characteristics,” IEEE Electron Device Letters, vol. 34, no. 7, pp. 885-887, Jul. 2013 [LINK[PDF] 

  21. K. L. Lin, T. H. Hou, Y. J. Lee, J. W. Chang, J. H. Lin, J. Shieh, C. T. Chou, T. F. Lei, W. H. Chang, W. Y. Jang, and C. H. Lin, "Switching mode and mechanism in binary oxide RRAM using Ni electrode," Jpn. J. Appl. Phys., vol. 52, 031801, Feb. 2013.  [LINK] [PDF] 

  22. C. L. Lo, T. H. Hou, M. C. Chen, and J. J. Huang, “Dependence of read margin on pull-up schemes in high-density one selector-one resistor (1S1R) crossbar array,” IEEE Trans. Elec. Dev., vol. 60, no. 1, pp.420-426, Jan. 2013[LINK] [PDF] 

  23. S. C. Wu, T. H. Hou, S. H. Chuang, H. C. Chou, T. S. Chao, and T. F. Lei, "Polycrystalline silicon thin-film transistor with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation," Solid-State Electron.vol. 78, pp. 11–16, Dec. 2012.  [LINK] [PDF]

  24. W. C. Luo, K. L. Lin, J. J. Huang, C. L. Lee, and T. H. Hou, “Rapid prediction of RRAM RESET-state disturb by ramped voltage stress,” IEEE Electron Device Lettersvol. 33, no. 4, pp.597-599, Apr. 2012[LINK] [PDF]

  25. J. J. Huang, T. H. Hou, C. W. Hsu, Y. M. Tseng, W. H. Chang, W. Y. Jang, and C. H. Lin, “Flexible one diode-one resistor crossbar resistive-switching memory,” Jpn. J. Appl. Phys., vol. 51, 04DD09, Apr. 2012.  [LINK] [PDF]

  26. J. T. Shaw, S. Q. Xu, S. Rajwade, T. H. Hou, and E. C. Kan “Redox molecules for a resonant tunneling barrier in nonvolatile memory,” IEEE Trans. Elec. Dev.vol. 58, no. 3, pp.826-834, Mar. 2012.  [LINK] [PDF]

  27. M. J. Yu, Y. H. Yeh, C. C. Cheng, C. Y. Lin, G. T. Ho, B. C. Lai, C. M. Leu, T. H. Hou, and Y. J.  Chan, “Amorphous InGaZnO thin-film transistors compatible with roll-to-roll fabrication at room temperature,” IEEE Electron Device Letters, vol. 33, no. 1, pp. 47-49, Jan. 2012. [LINK] [PDF]

  28. S. C. Wu, C. Lo, and T. H. Hou, “Novel two-bit-per-cell resistive-switching memory for low-cost embedded applications,” IEEE Electron Device Letters, vol. 32, no. 12, pp. 1662-1664, Dec. 2011.  [LINK] [PDF]

  29. J. Lee, J. J. Cha, S. Barron, D. A. Muller, R. B. van Doverc, E. K. Amponsaha, T. H. Hou, H. Raza, and E. C. Kan, “Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages,” Microelectronic Engineering, vol. 88, no. 12, pp. 3462-3465, Dec. 2011. [LINK] [PDF

  30.  J. J. Huang, Y. M. Tseng, C. W. Hsu, and T. H. Hou, “Bipolar nonlinear Ni/TiO2/Ni selector for 1S1R crossbar array applications,” IEEE Electron Device Letters, vol. 32, no. 10, pp.1427-1429, Oct. 2011. [LINK] [PDF]

  31. K. L. Lin, T. H. Hou, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, “Electrode dependence of filament formation in HfO2 resistive-switching memory,” J. Appl. Phys., vol. 109, no 8, 084104, Apr. 2011[LINK] [PDF

  32. T. H. Hou, K. L. Lin, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, “Evolution of RESET current and filament morphology in low-power HfO2 unipolar resistive switching memory, “ Appl. Phys. Lett., vol. 98, no. 10, 103511, Mar. 2011 (Also appeared in Virtual Journal of Nanoscale Science & Technology). [LINK] [PDF

  33. J. Shaw, Y. W. Zhong, K. Hughes, T. H. Hou, H. Raza, S. Rajwade, J. Bellfy, J. R. Engstrom, H. D. Abruña, and E. C. Kan “Integration of self-assembled redox molecules in flash memories,” IEEE Trans. Elec. Dev., vol. 58, no. 3, pp.826-834, Mar. 2011.  [LINK] [PDF

  34. S. H. Chuang, M. L. Hsieh, S. C. Wu, H. C. Lin, T. S. Chao, and T. H. Hou, “Fabrication and characterization of high-k dielectric nickel titanate thin films using a modified sol–gel method,” J. Am. Ceram. Soc., vol. 94, no. 1, pp. 250-254, 2011.  [LINK] [PDF

  35. J.-J. Huang, C.-W. Kuo, W.-C. Chang, and T.-H. Hou, “Transition of stable rectification to resistive-switching in Ti/TiO2/Pt oxide diode,” Appl. Phys. Lett., vol. 96, no. 26, 262901, Jun.  2010[LINK] [PDF

  36. C.-C. Lu, J.-J. Huang, W.-C. Luo, T.-H. Hou, and T.-F. Lei, “Characterization of highly strained nFET device performance and channel mobility with SMT,” J. Electrochem. Soc., vol. 157, no. 7, H705-H710, May. 2010. [LINK] [PDF]

  37. S.-H. Wu, C.-K. Deng, T.-H. Hou, and B.-S. Chiou, “Stability of La2O3 metal-insulator- metal capacitors under constant voltage stress,” Jpn. J. Appl. Phys., vol. 49, no. 4, 04DB16, Apr. 2010.  [LINK] [PDF]

  38. C.-C. Lu, J.-J. Huang, W.-C. Luo, T.-H. Hou, and T.-F. Lei, “Strained silicon technology: mobility enhancement and improved short channel effect performance by stress memorization technique on nFET devices,” J. Electrochem. Soc., vol. 157, no. 5, H497-H500, Mar. 2010.  [LINK] [PDF]

  39. J. Shaw, T. H. Hou, H. Raza, and E. C. Kan, “Statistical metrology of metal nanocrystal memories with 3-D finite-element analysis,” IEEE Trans. Elec. Dev., vol. 56, no. 8, p.1729, Aug. 2009.  [LINK] [PDF]

  40. C.-C. Lu, T.-F. Lei, T.-H. Hou, C.-H. Chien, M.H. Liao, T. L. Lee, and S. M. Jang, “An investigation of strain silicon technology on highly strained, highly scaled nFET devices,” Int. J. Electr. Eng., vol. 16, pp. 289-294, Aug. 2009.

  41. T. H. Hou, H. Raza, K. Afshari, D. J. Ruebusch, and E. C. Kan, 2008, Apr., “Nonvolatile memory with molecule-engineered tunneling barriers,” Appl. Phys. Lett., vol. 92, no. 15, 153109, Apr. 2008  (Top 20 most downloaded in APL, April 2008) (Also appeared in Virtual Journal of Nanoscale Science & Technology).  [LINK] [PDF]

  42. T. H. Hou, U. Ganguly, and E. C. Kan, 2007, Feb., “Fermi-level pinning in nanocrystal memories,” IEEE Electron Device Letters, vol. 28, no. 2, pp.103-106, Feb. 2007. [LINK] [PDF]

  43. U. Ganguly, C. Lee, T. H. Hou, and E. C. Kan, 2007, Jan., “Enhanced electrostatics for low-voltage operations in nanocrystal based nanotube/nanowire memories,” IEEE Trans. Nanotech., vol. 6, no. 1, pp. 22-27, Jan. 2007.  [LINK] [PDF]

  44. T. H. Hou, U. Ganguly, and E. C. Kan, 2006, Dec., “Programable molecular orbital states of C60 from integrated circuits,” Appl. Phys. Lett., vol. 89, no. 25, 253113, Dec. 2006.  (Also appeared in Virtual Journal of Nanoscale Science & Technology).  [LINK] [PDF]

  45. T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, 2006, Dec., “Design optimization of metal nanocrystal memory─Part I: nanocrystal array engineering,” IEEE Trans. Elec. Dev., vol. 53, no. 12, pp.3095-3102, Dec. 2006.  [LINK] [PDF]

  46. T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, 2006, Dec., “Design optimization of metal nanocrystal memory─Part II: gate stack engineering,” IEEE Trans. Elec. Dev., vol. 53, no. 12, pp. 3103-3109, Dec. 2006.   [LINK] [PDF]

  47. U. Ganguly, V. Narayanan, C. Lee, T. H. Hou, and E. C. Kan, 2006, Jun., “Three-dimensional analytical modeling of nanocrystal memory electrostatics,” J. Appl. Phys., vol. 99, no. 11, 114516, Jun. 2006. [LINK] [PDF]

  48. C. Lee, T. H. Hou, and E. C. Kan, 2005, Dec., “Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating gate,” IEEE Trans. Elec. Dev., vol. 52, no. 12, pp. 2697-2702, Dec. 2005. [LINK] [PDF]

  49. C.  Lee, U. Ganguly, V. Narayanan, T. H. Hou and E. C. Kan, 2005, Dec., “Asymmetric electric field enhancement in nanocrystal memories,” IEEE Electron Device Letter, vol. 26, no. 12, pp. 879-881, Dec. 2005. [LINK] [PDF]

  50. C. W. Yang, Y. K. Fang, S. F. Chen, C. S. Lin, C. Y. Lin, W. D. Wang, T. H. Chou, P. J. Lin, M. F. Wang, T. H. Hou, L. G. Yao, S. C. Chen and M. S. Liang, “Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application,” IEE Proc.-Circuits Devices System, vol. 152, no. 5, pp. 407-410, Oct. 2005. [LINK] [PDF]    

  51. C. M. Sparks, M. R. Beebe, J. Bennett, B. Foran, C. Gondran and A. Hou, “Characterization of high-k gate dielectric and metal gate electrode semiconductor samples with a total reflection X-ray fluorescence spectrometer,” Spectrochimica Acta. Part B, Atomic Spectroscopy, vol. 59, no. 8, pp. 1227-1234, Jul. 2004.  [LINK] [PDF] 

  52. J. J. Peterson, C. D. Young, J. Barnett, S. Gopalan, J. Gutt, C. H. Lee, H. J. Li, T. H. Hou, Y. Kim, C. Lim, N. Chaudhary, N. Moumen, B. H. Lee, G. Bersuker, G. A. Brown, P. M. Zeitzoff, M. I. Gardner, R. W. Murto, and H. R. Huff, “Subnanometer scaling of HfO2/metal electrode gate stacks,” Electrochem. Solid-State Lett., vol. 7, no. 8, G164-G167, Jun. 2004.  [LINK] [PDF] 

  53. H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C. D.Young, P.M. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner and R.W. Murto, “Integration of high-k gate stacks into planar scaled CMOS integrated circuits,” Microelectronic Engineering, vol. 69, pp.152-167, Sep. 2003.  [LINK] [PDF] 

  54. C. W. Yang, Y. K. Fang, C. H. Chen, S. F. Chen, C. Y. Lin, C. S. Lin, M. F. Wang, Y. M. Lin, T. H. Hou, C. H. Chen, L. G. Yao, S. C. Chen, and M. S. Liang, “Effect of polycrystalline-silicon gate types on the opposite flatband voltage shift in n-type and p-type metal-oxide-semiconductor field-effect transistors for high-k-HfO2 dielectric,” Appl. Phys. Lett., vol. 83, no. 2, pp. 308 - 310, Jul 2003.  [LINK] [PDF] 

  55. C.-W. Yang, Y.-K. Fang, S.-F. Chen, M.-F. Wang, T.-H. Hou, Y.-M. Lin, L.-G. Yao, S.-C. Chen, and M.-S. Liang, “HfO2/HfSixOy high-K gate stack with very low leakage current for low-power poly-Si gated CMOS application,” Electron. Lett., vol. 39, no. 8, pp. 692-694, Apr. 2003.  [LINK] [PDF]

  56. C.-W. Yang, Y.-K. Fang, S.-F. Chen, C.-Y. Lin, M.-F. Wang, Y.-M. Lin, T.-H. Hou, L.-G. Yao, S.-C. Chen, and M.-S. Liang, “Effective improvement of high-k Hf-silicate/silicon interface with thermal nitridation,” Electron. Lett., vol. 39, no. 5, pp.421–422, Mar. 2003.  [LINK] [PDF]

  57. A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, “Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics,” IEEE Electron Device Letters, vol.24, no.2, pp. 87-89, Feb. 2003.  [LINK] [PDF]

  58. J. Bennett, C. Gondran, C. Sparks, P.Y. Hung, A. Hou, “SIMS depth profiling of advanced gate dielectric materials,” Appl. Surface Science, vol. 203-204, pp. 409-417, Jan. 2003.  [LINK] [PDF]

  59. C.-W. Yang, Y.-K. Fang, C.-H. Chen, W.-D. Wang, T.-Y. Lin M.-F. Wang, T.-H. Hou, J.-Y. Cheng, L.-G. Yao, S.-C. Chen, C.-H. Yu, and M.-S. Liang, “Dramatic reduction of gate leakage current in 1.61 nm HfO2 high-k dielectric poly-silicon gate with Al2O3 capping layer,” Electron. Lett., vol. 38, no. 20, pp. 1223–1225, Sep. 2002.  [LINK] [PDF]

  60. C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsai, C. N. Chang, T. H. Hou, M. F. Wang, M. C. Yu, C. L. Lin, S. C. Chen, C. H. Yu and M. S. Liang, “Improved current drivability and poly-gate depletion of submicron PMOSFET with poly-SiGe gate and ultra-thin nitride gate dielectric,” Solid-State Electronics, vol. 46, no. 4, pp. 597-599, Apr. 2002.  [LINK] [PDF]

  61. C.H. Chen, Y.K. Fang, C.W. Yang, S.F. Ting, Y.S. Tsair, M.F. Wang, T. H. Hou, M.C. Yu, S.C. Chen, S. M. Jang, D.C.H. Yu and M.S. Liang, “To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post deposition treatment,” IEEE Trans. of Electron Device, vol. 48, no.12, pp.2769-2776, Dec. 2001.  [LINK] [PDF]

  62. C.H. Chen, Y.K. Fang, C.W. Yang, S.F. Ting, Y.S. Tsair, T. H. Hou, M.F. Wang, M.C. Yu, S.C. Chen, S. M. Jang, D.C.H. Yu and M.S. Liang, , "Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion," IEEE Electron Device Letters, vol.22, no.8, pp.378-380, Aug 2001.  [LINK] [PDF]

  63. T. H. Hou, T. F. Lei, and T. S. Chao, “Improvement of junction leakage of nickel silicided junction by Ti-capping layer,” IEEE Electron Device Letters, vol. 20, no. 11, p.572, 1999.  [LINK] [PDF

   Book Chapter [Return to Top]
  1. T. H. Hou, “Metal-oxide resistive-switching RAM technology,” McGraw-Hill 2011 Yearbook of Science and Technology, ISBN 9780071763714.

   Conference [Return to Top]
  1. (Invited paper) I-T. Wang, T. Chou, L.-W. Chiu, C.-C. Chang, and T.-H. Hou, "Development of three-dimensional synaptic device and neuromorphic computing hardware," International Conference on Solid-State and Integrated Circuit Technology (ICSICT) 2016, Hangzhou, China, October 25-28, 2016.

  2. C.-C. Wan, C.-J. Su, S.-H. Hsu, G.-L. Luo, T.-H. Hou, W.-F. Wu, and W.-K. Yeh, "Suspended Ge gate-all-around nanowire FETs with selective etching technique," International Conference on Solid State Devices and Materials (SSDM) 2016, Tsukuba, Japan, Sep. 26-29, 2016.

  3. (Invited paper) C.-P. Lin, C.-T. Lin, P.-S. Liu, M.-J. Yu, and T.-H. Hou "Grain size and plasma doping effects on CVD-based 2D transition metal dichalcogenide," IEEE International Conference on Nanotechnology (IEEE NANO 2016), Sendai City, Miyagi, Japan, August 22-25, 2016.

  4. C.-C. Wan, G.-L. Luo, S.-H. Hsu, G.-D. Hung, C.-L. Chu, T.-H. Hou, C.-J. Su, S.-H. Chen, W.-F. Wu, and W.-K. Yeh, " Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si," IEEE Silicon Nanoelectronics Workshop (SNW) 2016, Honolulu, HI, USA, Jun. 12-13, 2016.

  5. C.-H. Lu, M.-J. Yu, Y.-H. Chang, Y.-H. Lai, P.-S. Liu, T.-H. Hou and T.-M. Pan, "Sub-0.5 V low-temperature a-IGZO ion-sensitive FET," International Symposium on Next-Generation Electronics (ISNE) 2016, Hsinchu, Taiwan, May 4–6, 2016.

  6. M.-J. Yu, R.-P. Lin, Y.-H. Chang, and T.-H. Hou, "Reliable high-voltage amorphous InGaZnO TFT for monolithic 3D integration," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2016, Hsinchu, Taiwan, Apr. 25–27, 2016. [LINK[PDF]

  7. Y.-J. Lee, F.-J. Hou, S.-S. Chuang, F.-K. Hsueh, K.-H. Kao, P.-J. Sung, W.-Y. Yuan, Y.-C. Lu, K.-L. Lin, C.-T. Wu, J.-Y. Yao, H.-C. Chen, Henry J. H. Chen, T.-S. Chao, T.-Y. Tseng, W.-F. Wu, T.-H. Hou, W. -K. Yeh, “Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology,” International Electron Devices Meeting (IEDM) 2015, pp. 382-385, Washington, DC, USA, Dec. 7-9, 2015. (2015 IEDM Highlighted Paper) [LINK [PDF] 

  8. C.-T. Lin, C.-P. Lin, P.-S. Liu, L.-J. Li, and T.-H. Hou, “Improving contact resistance of 2D MoS2 transistor using H2 plasma treatment,” International Electron Devices and Materials Symposia (IEDMS) 2015, Tainan, Taiwan, Nov. 19–20, 2015.

  9. L.-W. Chiu, I-T. Wang, and T.-H. Hou, “Influence of input strength on retention characteristics in Ta/TaOx/TiO2/Ti synaptic device,” International Electron Devices and Materials Symposia (IEDMS) 2015, Tainan, Taiwan, Nov. 19–20, 2015.

  10. P.-Y. Chen, B. Lin, I-T. Wang, T.-H. Hou, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, and S. Yu, "Mitigating effects of non-ideal synaptic device characteristics for on-chip learning," International Conference On Computer Aided Design (ICCAD) 2015, pp. 194-199, Austin, TX, USA, Nov. 2-6, 2015. [LINK [PDF] 

  11. (Invited paper) T. H. Hou, "3D RRAM-based synaptic network with low programming energy," 5th Stanford-imec International RRAM Workshop, Leuven, Belgium, September 24–25, 2015.

  12. B. Hudec, I-T. Wang, W.-L. Lai, C.-C. Zhang, T.-H. Hou, P. Jančovič, K. Fröhlich, and M. Micušík, "Interface engineered HfO2-based 3D vertical resistive random access memory with forming-free operation," International Conference on Solid State Devices and Materials (SSDM) 2015, Sapporo, Japan, Sep. 27-30, 2015.

  13. C.-P. Lin, P.-S. Liu, L.-S. Lyu, M.-Y. Li, C.-C. Cheng, T.-H. Lee, W.-H. Chang, L.-J. Li, and T.-H. Hou, "N-type doping effect of transferred MoS2 and WSe2 monolayer," International Conference on Solid State Devices and Materials (SSDM) 2015, Sapporo, Japan, Sep. 27-30, 2015.

  14. K. Fröhlich, P. Jančovič, J. Dérer, E. Dobročka, B. Hudec, P. Calka, C. Walczyk, G. Niu, T. Schroeder, I-T. Wang, C. W. Hsu, and T.-H. Hou "Atomic layer deposited HfO2 films for next generation resistive switching memory," International Baltic Conference on Atomic Layer Deposition 2015, Tartu, Estonia, Sep. 28–29, 2015.

  15. Y.-H. Lai and T.-H. Hou, "Oxygen plasma-treated ALD ZnO thin film transistors," International Display Manufacturing Conference (IDMC) 2015, Taipei, Taiwan, Aug. 25-28, 2015.

  16. R. Lo, P.-Y. Du, T.-H. Hsu, C.-J. Wu, J.-Y. Guo, C.-M. Cheng, H.-T. Lue, Y.-H. Shih, T.-H. Hou, K.-Y. Hsieh, and C.-Y. Lu, “A Study of blocking and tunnel oxide engineering on double-trapping (DT) BE-SONOS performance” 7th International Memory Workshop (IMW), Monterey, CA, May 17–20, 2015.

  17. C.-P. Lin, L.-S. Lyu, C.-T. Lin, P.-S. Liu, W.-H. Chang, L.-J. Li, and T.-H. Hou, "Grain size effect of monolayer MoS2 transistors characterized by second harmonic generation mapping," International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2015, Hsinchu, Taiwan, Jun. 29–Jul. 2, 2015.

  18. T. Chou, J.-C. Liu, L.-W. Chiu, I.-T. Wang, C.-M. Tsai, and T.-H. Hou, "Neuromorphic pattern learning using HBM electronic synapse with excitatory and inhibitory plasticity," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2015, Hsinchu, Taiwan, Apr. 27–29, 2015. [LINK[PDF]

  19. (Invited paper) T. H. Hou, "3D RRAM technology for electronic synapses applications," China Semiconductor Technology International Conference (CSTIC 2015), Shanghai, China, March 15–16, 2015.

  20. I.-T. Wang, Y.-C. Lin, Y.-F. Wang, C.-W. Hsu, and T.-H. Hou, "3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation," International Electron Devices Meeting (IEDM) 2014, pp. 665-668, San Francisco, CA, USA, Dec. 15-17, 2014. [LINK [PDF

  21. P.-S. Liu, C.-H. Chen, W.-T. Hsu, C.-P. Lin, T.-P. Lin, L.-J. Chi, C.-Y. Chang, S.-C. Wu, W.-H. Chang, L.-J. Li and T.-H. Hou, "Fast visible-light phototransistor using CVD-synthesized large-area bilayer WSe2," International Electron Devices Meeting (IEDM) 2014, pp. 132-135, San Francisco, CA, USA, Dec. 15-17, 2014. [LINK [PDF]

  22. T.-P. Lin, Y.-F. Wang, and T.-H. Hou, “Simulation of nonpolar resistive-switching memory,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.

  23. L.-J. Chi, Y.-H. Chang, and T.-H. Hou, “Demonstrating high-performance a-InGaZnO inverter at room-temperature for BEOL applications,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.

  24.  C.-P. Lin, P.-S. Liu, C.-Y. Chang, S.-C. Wu, L.-J. Li, and T.-H. Hou, “Effect of HfO2 gate dielectrics on WSe2 transistors,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.

  25. W.-L. Lai, C.-T. Chou, C.-W. Hsu, T.-P. Lin, B. Hudec, and T.-H. Hou, “Crossbar array of TaOx/TiO2 bilayer RRAM,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.

  26. C.-C. Chang, J.-C. Liu, and T.-H. Hou, “RRAM crossbar array analysis with line resistance,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.

  27. (Invited paper) T. H. Hou, "Statistical study and rapid prediction methodology of RRAM SET speed-disturb dilemma," 2014 Taiwan ESD and Reliability Conference (2014 T-ESDA), Hsinchu, Taiwan, Nov. 11–13, 2014.

  28.  W.-L. Lai, C.-T. Chou, C.-W. Hsu, J.-C. Liu, B. Hudec, C.-H. Ho, W.-Y. Jang, C.-H. Lin, and T. H. Hou, "Interface engineering in homogeneous barrier modulation RRAM for 3D vertical memory applications," International Conference on Solid State Devices and Materials (SSDM) 2014, Tsukuba, Japan, Sep. 8-11, 2014.

  29. (Invited paper) T. H. Hou, "Emerging RRAM for 3D storage-class memory," China Semiconductor Technology International Conference (CSTIC 2014), Shanghai, China, March 16 –17, 2014.

  30. J.-C. Liu, I.-T. Wang, C.-W. Hsu, W.-C. Luo, and T.-H. Hou, "Investigating MLC variation of filamentary and non-filamentary RRAM," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan, Apr. 28–30, 2014. [LINK[PDF]

  31. L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T.-H. Hou, H.-S. P. Wong, and Y. Nishi, "Improved multi-level control of RRAM using pulse-train programming," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan, Apr. 28–30, 2014. (Best Student Paper Award) [LINK[PDF] 

  32. C. W. Hsu, C. C. Wan, I. T. Wang, M. C. Chen, C. L. Lo, Y. J. Lee, W. Y. Jang, C. H. Lin, and T. H. Hou, "3D vertical TaOx/TiO2 RRAM with over 103 self-rectifying ratio and sub-uA operating current," International Electron Devices Meeting (IEDM) 2013, pp. 264-268, Washington, DC, USA, Dec. 9-11, 2013. [LINK [PDF] 

  33. Y. Deng, H.-Y. Chen, B. Gao, S. Yu, S.-C. Wu, L. Zhao, B. Chen, Z. Jiang, T.-H. Hou, Y. Nishi, J. Kang, and H.-S. P. Wong, "Design and optimization methodology for 3D RRAM arrays," International Electron Devices Meeting (IEDM) 2013, pp. 629-632, Washington, DC, USA, Dec. 9-11, 2013. [LINK[PDF] 

  34.  (Invited paper) T. H. Hou, C. W. Hsu, and I. T. Wang, "Advance of 3D-stackable binary-oxide ReRAM for storage-class memory applications," AVS 60th International Symposium and Exhibition (AVS 2013), Long Beach, California, USA, October 28–30, 2013. 1.    

  35. (Invited paper) T. H. Hou, S. C. Wu, M. J. Yu, P. S. Liu, and L. J. Chi, "Low-cost embedded RRAM technology for system-on-plastic integration using a-IGZO TFTs," International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD '13), Kyoto, Japan, July 2 – 5, 2013. [LINK[PDF] 

  36. C. W. Hsu, I. T. Wang, C. L. Lo, M. C. Chiang, W. Y. Jang, C. H. Lin and T. H. Hou, "Self-rectifying bipolar TaOx/TiOx RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory," Symposium on VLSI Technology, Kyoto, Japan, Jun. 11-13, 2013. [LINK[PDF] 

  37. (Invited paper) T. H. Hou, S. C. Wu, M. J. Yu, and C. Lo, "Logic/RRAM hybrid thin-film transistor technology," Symposium on Nano Device Technology (SNDT) 2013, Hsinchu, Taiwan, Apr. 25-26, 2013. 

  38. P. S. Liu, I. T. Wang, S. C. Wu and T. H. Hou, "Characteristics of bipolar Ta/TaOX/Pt resistive-switching memory," Symposium on Nano Device Technology (SNDT) 2013, Hsinchu, Taiwan, Apr. 25-26, 2013. 

  39. C. T. Chou, I. T. Wang, C. W. Hsu, and T. H. Hou, "Mechanism of RRAM retention failure by temperature acceleration," Symposium on Nano Device Technology (SNDT) 2013, Hsinchu, Taiwan, Apr. 25-26, 2013. 

  40. C. L. Lo, M. C. Chen, J. J. Huang, and T. H. Hou, "On the potential of CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2013, Hsinchu, Taiwan, Apr. 22–24, 2013. [LINK[PDF] 

  41. S. C. Wu, H. T. Feng, M. J. Yu, I. T. Wang, and T. H. Hou, "Multi-bit-per-cell a-IGZO TFT resistive-switching memory for system-on-plastic applications," International Electron Devices Meeting (IEDM) 2012, San Francisco, CA, USA, Dec. 10-12, 2012. [LINK] [PDF] 

  42. W. C. Luo, J. C. Liu, H. T. Feng, Y. C. Lin, J. J. Huang, K. L. Lin, and T. H. Hou, "RRAM SET speed-disturb dilemma and rapid statistical prediction methodology," International Electron Devices Meeting (IEDM) 2012, San Francisco, CA, USA, Dec. 10-12, 2012. [LINK] [PDF] 

  43. M. C. Chen, C. L. Lo, and T. H. Hou, "Effect of one selector-one resistor 1S1R characteristics and read voltage on high-density RRAM array analysis," International Electron Devices and Materials Symposia (IEDMS) 2012, Kaohsiung, Taiwan, Nov. 29 – Nov. 30, 2012.

  44. L. J. Chi, S. C. Wu, and T. H. Hou, "High-performance a-InGaZnO TFT fabricated at room temperature with low operating voltage," International Electron Devices and Materials Symposia (IEDMS) 2012, Kaohsiung, Taiwan, Nov. 29 – Nov. 30, 2012.

  45. Y. F. Wang, H. T. Feng, and T. H. Hou, "Numerical RRAM simulation based on percolation theory," International Electron Devices and Materials Symposia (IEDMS) 2012, Kaohsiung, Taiwan, Nov. 29 – Nov. 30, 2012.

  46. Y. C. Lin, W. C. Luo, J. C. Liu, and T. H. Hou, "Rapid prediction of RESET-state disturb in TiN/Ti/HfO2/TiN RRAM," International Electron Devices and Materials Symposia (IEDMS) 2012, Kaohsiung, Taiwan, Nov. 29 – Nov. 30, 2012.

  47. C. W. Hsu, C. L. Lo, I. T. Wang, and T. H. Hou, " High-density 1S1R flexible bipolar resistive-switching memory," International Conference on Solid State Devices and Materials (SSDM) 2012, Kyoto, Japan, Sep. 25-27, 2012. [PDF]

  48. I. T. Wang, C. W. Hsu, and T. H. Hou, "Stable rectification and self-compliance resistive switching in Fe/TiO2/Pt MIM diode," Symposium on Nano Device Technology (SNDT) 2012, Hsinchu, Taiwan, Apr. 26-27, 2012. 

  49. S. C. Wu, C. Lo, and T. H. Hou, "Logic/resistive-switching hybrid transistor for two-bit-per-cell storage," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2012, Hsinchu, Taiwan, Apr. 23–25, 2012. [LINK] [PDF]

  50. J. J. Huang, Y. M. Tseng, W. C. Luo, C. W. Hsu, and T. H. Hou, “One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications,” International Electron Devices Meeting (IEDM) 2011, Washington, DC, USA, Dec. 5-7, 2011.  [LINK] [PDF] 

  51.  K. L. Lin, T. H. Hou, Y. J. Lee, J. H. Lin, J. W. Chang, J. Shieh, C. T. Chou, W. H. Chang, W. Y. Jang, and C. H. Lin, “Low-IRESET unipolar HfO2 RRAM and tunable resistive-switching mode via interface engineering,” International Semiconductor Device Research Symposium (ISDRS), College Park, MA, USA, December 9-11, 2011. [LINK] [PDF]

  52. S. C. Wu, T. H. Hou, S. H. Chuang, H. C. Chou, T. S. Chao, and T. F. Lei, “Improvement of polycrystalline silicon thin-film transistors with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation,” International Semiconductor Device Research Symposium (ISDRS), College Park, MA, USA, December 9-11, 2011. [LINK] [PDF]

  53. C. L. Lo, J. J. Huang, Y. M. Tseng, and T. H. Hou, “Read margin analysis on 1S1R crossbar RRAM — a study of numerical circuit simulation”, International Electron Devices and Materials Symposia (IEDMS) 2011, Nov. 17 – Nov. 18, 2011.

  54. W. C. Huang, W. C. Luo, and T. H. Hou, “Fully CMOS-compatible chemoreceptive neuron MOS (CυMOS) transistor for fluid sensing”, International Electron Devices and Materials Symposia (IEDMS) 2011, Nov. 17 – Nov. 18, 2011.

  55. C. W. Hsu, J. J. Huang, Y. M. Tseng, T. H. Hou, W. H. Chang, W. Y. Jang, and C. H. Lin, “Flexible one diode-one resistor crossbar resistive-switching memory,” International Conference on Solid State Devices and Materials (SSDM) 2011, Nagoya, Japan, Sep. 28-30, 2011. [PDF]

  56. K. L. Lin, Y. M. Tseng, J. H. Lin, J. Shieh, Y. J. Lee, T. H. Hou, and T. F. Lei, “High- performance Ni/SiO2/Si programmable metallization cell,” IEEE International NanoElectronics. Conference (INEC) 2011, Taoyuan, Taiwan, Jun. 21–24, 2011. [LINK] [PDF]

  57. K. L. Lin, T. H. Hou, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, “Comprehensive study on filament morphology in low-power unipolar Ni/HfO2/Si RRAM,” Symposium on Nano Device Technology (SNDT) 2011, Hsinchu, Taiwan, Apr. 22-23, 2011.

  58. S. J. Fu, S. C. Wu, and T. H. Hou, “Aluminum-doped zinc oxide thin-film transistors with high-k gate dielectrics,” Symposium on Nano Device Technology (SNDT) 2011, Hsinchu, Taiwan, Apr. 22-23, 2011.

  59. C. W. Hsu, C. W. Kuo, J. J. Huang, and T. H. Hou, “Development of 1D-1R TiO2 RRAM compatable with room-temperature fabrication,” International Electron Devices and Materials Symposia (IEDMS) 2010, Nov. 18–19, 2010.

  60. K. L. Lin, J. H. Lin, J. Shieh, C. T. Chou, Y. J. Lee, Y. M. Li, and T. H. Hou, “Silicon-compatable unipolar-switching Ni/HfO2/Si RRAM,” International Electron Devices and Materials Symposia (IEDMS) 2010, Taoyuan, Taiwan, Nov. 18–19, 2010.

  61. W. C. Chang, J. J. Huang, C. W. Kuo, K. L. Lin, and T. H. Hou, ”Doping effect and thermal instability of Ti:NiO resistive switching random access memory,” International Electron Devices and Materials Symposia (IEDMS) 2010, Taoyuan, Taiwan, Nov. 18–19, 2010.

  62. S. Rajwade, W. K. Yu, S. Xu. T. H. Hou, G. E. Suh, and E. Kan, “Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS flash,” 2010 IEEE International SOC Conference (SOCC 2010), Las Vegas, NV, USA, 27-29 Sept. 2010.

  63. C. W. Kuo, J. J. Huang, W. C. Chang, and T. H. Hou, “One-diode-one-resistor titanium-oxide RRAM fabricated at room temperature,” International Conference on Solid State Devices and Materials (SSDM) 2010, Tokyo, Japan, Sep. 22-24, 2010. [PDF]

  64. S. C. Wu, T. H. Hou, S. H. Chuang, H. C. Chou, P. Y. Kuo, T. S. Chao, T. F. Lei, “High-performance polycrystalline silicon thin-film transistor with nickel-titanium oxide by sol-gel spin-coating and fluorine implantation,” International Conference on Solid State Devices and Materials (SSDM) 2010, Tokyo, Japan, Sep. 22-24, 2010.

  65. W.-C. Chang, J.-J. Huang, C.-W. Kuo, G.-L. Lin, and T.-H. Hou, “Improvement of NiO resistance random access memory by high-temperature reactive sputtering,” Symposium on Nano Device Technology (SNDT) 2010, Hsinchu, Taiwan, May 4-5, 2010.

  66. S.-H. Wu, C.-K. Deng, T.-H. Hou, and B.-S. Chiou “Stability and degradation mechanism of La2O3 metal-insulator-metal capacitors under constant voltage stress,” 217th Electrochemical Society (ECS) Meeting, Vancouver, Canada, Apr. 25-30, 2010.

  67.  J.-J. Huang, G.-L. Lin, C.-W. Kuo, W.-C. Chang, and T.-H. Hou, “Room-temperature TiOx oxide diode for 1D1R resistance-switching memory,” International Semiconductor Device Research Symposium (ISDRS), College Park, MA, USA, Dec. 9-11, 2009.  [LINK] [PDF]

  68. S.-C. Wu, C. L., C.-K. Deng, T.-S. Chao, S.-H. Chuang, T.-H. Hou, and T.-F. Lei, “Characterization of polycrystalline silicon thin-film transistors with nickel-titanium oxide films by sol-gel spin-coating method,” International Electron Devices and Materials Symposia (IEDMS) 2009, Taoyuan, Taiwan, Nov. 19–20, 2009.

  69. J.-J. Huang, G.-L. Lin, C.-W. Kuo, W.-C. Chang, and T.-H. Hou, “Room-temperature TiOx oxide diode for 1D1R resistance-switching memory,” International Electron Devices and Materials Symposia (IEDMS) 2009, Taoyuan, Taiwan, Nov. 19–20, 2009.

  70. J. Shaw, T. H. Hou, H. Raza, and E. C. Kan, “3D finite-element analysis of metal nanocrystal memories variations,” 13th International Workshop on Computational Electronics (IWCE) 2009, pp. 141-143, Beijing, China, May 27-30, 2009.  [LINK] [PDF]

  71. H. Raza, T. Raza, T. H. Hou, and E. C. Kan, "Electronic-structure modulation transistor: A new switch with few kT supply voltage," APS March Meeting, Pittsburgh, PA, USA, Mar. 16–20, 2009 (Also appeared in arXiv:0812.0123).

  72. J. Lee, J. J. Cha, S. C. Barron, D. A. Muller, R. B. van Dover, E. K. Amponsah, T.-H. Hou, H. Raza, and E. C. Kan, “Low-temperature planar polysilicon TFT flash memory cell with single and double metal nanocrystals and Al2O3/(Ti,Dy)xOy dielectric layers for 3D integration,” IEEE International SOI Conference 2008, pp. 39-40, New Paltz, NY, USA, Oct. 06-09, 2008. [LINK] [PDF]

  73. T. H. Hou, H. Raza, K. Afshari, D. J. Ruebusch, and E. C. Kan, 2008, “Heterogeneous integration of molecules in nonvolatile memory,” 66nd Device Research Conference, pp. 275-276, Santa Babara, CA, USA, Jun. 23-25, 2008.  [LINK] [PDF]

  74. J. Lee, S. C. Barron, R. B. van Dover, E. K. Amponsah, T.-H. Hou, H. Raza, and E. C. Kan, “Planar poly-silicon TFT low-voltage flash memory cell with Al2O3 tunnel dielectric and (Ti,Dy)O control dielectric for three-dimensional integration,” 66nd Device Research Conference, pp. 279-280, Santa Babara, CA, USA, Jun 23-25, 2008.  [LINK] [PDF]

  75. J. Lee, S. C. Barron, R. B. van Dover, E. K. Amponsah, T.-H. Hou, H. Raza, and E. C. Kan, “Highly stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltage,” 2008 E-MRS meeting, Strasbourg, France, May 26 - 30, 2008.

  76. T. H. Hou, J. Lee, J. T. Shaw, and E. C. Kan, 2008, ”Flash memory scaling: from material selection to performance improvement,” 2008 MRS spring meeting, San Francisco, CA, USA, Mar. 24 – 28, 2008. (Invited paper, Symposium F)  [PDF]

  77. T. H. Hou, C. Lee, and E. C. Kan, 2007, “Modeling of multi-layer nanocrystal memory,” 65nd Device Research Conference, pp.221-222, Notre Dame, IN, USA, Jun. 18-20, 2007. [LINK] [PDF]

  78. U. Ganguly, T. H. Hou, and E. C. Kan, 2006, ”Quantum transport and trap effects in tunneling rate measurements of metal nanocrystal based carbon nanotube memory,” 2006 MRS fall meeting , Boston, MA, USA, Nov. 27 – Dec. 1, 2006.

  79. U. Ganguly, T. H. Hou, and E. C. Kan, 2006, ”Process integration of composite high-k tunneling dielectric for nanocrystal based carbon nanotube memory,” 2006 MRS fall meeting , Boston, MA, Nov. 27 – Dec. 1, 2006.

  80. T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, 2006, “3-D electrostatic modeling and impact of high-k control oxide in metal nanocrystal memory,” 64nd Device Research Conference, pp.271-272, University Park, PA, USA, Jun. 26-28, 2006.  [LINK] [PDF]

  81. C. Lee, T. H. Hou, and E. C. Kan, 2005, “Metal nanocrystal/nitride heterogeneous-stack floating gate memory,” 63nd Device Research Conference, pp. 97-98, Santa Babara, CA, USA, Jun. 20-22, 2005. [LINK] [PDF]

  82. T. H. Hou, M. F. Wang, K. L. Mai, Y. M. Lin, M. H. Yang, L. G. Yao, Y. Jin, S. C. Chen, and M. S. Liang,  “Direct determination of interface and bulk traps in stacked HfO2 dielectrics using charge pumping method,” International. Reliability Physics Symposium (IRPS), pp. 581-582, Phoenix, AZ, USA, Apr. 25-29, 2004.  (cited 7 times) [LINK] [PDF]

  83. C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, , Y.H. Chiu., H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and, M.-S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application,” Symposium on VLSI Technology, pp. 56-57, Honolulu, HI, USA, Jun. 15-17, 2004.  [LINK] [PDF]

  84. M. F. Wang, T. H. Hou, K. L. Mai, P. S. Lim, L. G. Yao, Y. Jin, S. C. Chen and M. S. Liang, “Electrical performance improvement in SiO2/HfSiO high-k gate stack for advanced low power device application,” IEEE Int. Conference on Integrated Circuit Design and Technology, pp. 283-286, Austin, TX, USA, May 17-20, 2004. [LINK] [PDF]

  85. W. H. Wu, M. F. Wang, T. H. Hou, L. G. Yao, Y. Jin. S. C. Chen, M. S. Liang, and M. C, Chen, “Effects of base oxide thickness in HfSiO/SiO2 high-k gate stacks,” 11th IEEE Int. Symposium on the physical and failure analysis of integrated circuits, pp. 25-28, Hsinchu, Taiwan, Jul. 5-8, 2004.  [LINK] [PDF]

  86. H.C. Wang, S. J. Chen; M. F. Wang, P. Y. Tsai, C. W. Tsai, T. W. Wang, S. M. Ting, T. H. Hou, P. S. Lim, H. J. Lin, Y. Jin, H. J. Tao, S. C. Chen, C.H. Diaz, M.-S Liang, and C. Hu; “Low power device technology with SiGe channel, HfSiON, and poly-Si gate,” International Electron Devices Meeting, pp. 161-164, San Francisco, CA, USA, Dec. 13-15, 2004. [LINK] [PDF]

  87. C. D. Young, A. Kerber, T. H. Hou, E. Cartier, G. A. Brown, G. Bersuker, “Charge trapping and electron mobility degradation in MOCVD hafnium silicate gate dielectric stack structures,” 204nd ECS meeting, Orlando, FL, USA, Oct. 12-16, 2003.

  88. T. H. Hou, J. Gutt, C. Lim, S. Marcus, C. Pomarede, M. Gardner, R. Murto, and H. R. Huff, “Improved scalability of high-k gate dielectrics by using Hf-Aluminates,” 202nd ECS meeting, Salt Lake City, UT, USA, Oct. 20-24, 2002.

  89. C. Lim, Y. Kim, A. Hou, J. Gutt, S. Marcus, C. Pomarede, L. Chen, G. Bease, J. Tamim, N. Chaudhary, G. Bersuker, J. Barnett, C. Young, P. Zeitzoff, G. Brown, M. Gardner, R. Murto, and H. Huff, “Effect of deposition sequence and plasma treatment on ALCVD HfO2 n-MOSFET properties,” 202nd ECS meeting, Salt Lake City, UT, USA, Oct. 20-24, 2002.

  90. P.Y. Hung, B. Foran, A. Hou, X. Zhang, and C. Oroshiba, “Non-contact electrical characterization of high-dielectric-constant (high-k) materials,” 202nd ECS meeting, Salt Lake City, UT, USA, Oct. 20-24, 2002.43.    

  91. Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H. J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, A. Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, “Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode,” International Electron Devices Meeting, pp. 455-458, Washington, DC, USA,, Dec. 2-5, 2001. [LINK] [PDF]

  92. M. C. Yu, H. T. Huang, C. H. Chen, M. F. Wang, T. H. Hou, Y. M. Lin, S. M. Jang, C. H. Diaz, J. Sun, Y. K. Fang, S. C. Chen, C. H. Yu, and M. S. Liang “Base oxide scaling limit of thermally-enhanced remote plasma nitridation (TE-RPN) process for ultra-thin gate dielectric formation,” IEEE International Symposium on Semiconductor Manufacturing, pp. 179-182, San Jose, CA, USA, Oct. 8-10, 2001.  [LINK] [PDF]

  93. H. L. Sun, H. M. Jao, H. T. Huang, J. Y. Pan, T. H. Hou, S. Chen, S. Ramamurthy, E.  Chiao, D. Wilusz, and A. Chen “Spike anneal qualification for 0.13 μ m USJ technology on Radiance Centura”, 9th Int. Conf. Adv. Thermal Processing of Semiconductors. RTP 2001, pp. 246-249, Anchorage, AK, USA, Sep. 25-29, 2001.  [LINK] [PDF]

  94. M. F. Wang, C. H. Chen, M. C. Yu, T. H. Hou, Y. M. Lin, S. C. Chen, Y. K. Fang, C. H. Yu, and M. S. Liang, “Ultrathin ox/nitride gate stack for subuquarter-micro CMOS devices prepared by RTCVD,” IEEE International Symposium on VLSI Technology, Systems, and Applications, pp. 208-211, Hsinchu, Taiwan, Apr. 18-20, 2001. [LINK] [PDF]
     

   Media Coverage [Return to Top]
  1. "Slideshow: 2015 IEDM Preview", Solid-State Technology, Dec. 7, 2015. [LINK]

  2. "3D Non-Volatile Memory at IEDM 2013," EE Times, Dec. 31, 2013.  [LINK]

  3. "ReRAM Is Memory Focus at IEDM," EE Times, Sep. 30, 2013. [LINK]

  4. "Cheaper substrates made of oxide materials," Newswise, July 27, 2010. [LINK]

  5. "Buckyballs to boost flash memory," IEEE Spectrum, vol. 45, no. 6, p. 20, Jun. 2008. [LINK[PDF]

  6. "Nanoelectronics: Flash at the end of the tunnel," Nature Nanotechnology, May 2, 2008. [LINK]

  7. "Buckyballs give flash a boost," Naturevol. 452, p. 921, Apr. 2008. [LINK[PDF]

  8. "Buckyballs boost flash memory," Physics arXiv blog, April 1, 2008. [LINK]


   US Patent [Return to Top]

  1. T.-H. Hou, C.-W. Hsu, and M.-C. Chen, "Resistive memory apparatus and write-in method thereof," US Patent 9,269,434, Feb. 23, 2016.

  2. T. H. Hou, C. W. Hsu, and I. Ting Wang, "Self-rectifying RRAM cell structure and 3D crossbar array architecture thereof", US Patent 9,059,391, June 16, 2015.
  3. T. H. Hou, and S. C. Wu, “Multi-bit resistive switching memory cell and array”, US Patent 8,687,432, Apr. 1, 2014.

  4. E. C. Kan, and T. H. Hou, “Nonvolatile memory and methods for manufacturing the same with molecule-engineered tunneling barriers”, US Patent 8,542,540, Sep. 24, 2013.

  5. M. F. Wang, T. H. Hou, K. L. Mai, L. G. Yao, and S. C. Chen, “High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics”, US Patent 7,303,996, Dec. 4, 2007.

  6. T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual-gate structure and method of fabricating integrated circuits having dual-gate structures”, US Patent 7,271,450, Sep. 18, 2007

  7. M. F. Wang, C. L. Chen, C. W. Yang, C. C. Chen, T. H. Hou, Y. M. Lin, L. G. Yao, and S. C. Chen, “Method and structure for forming high-k gates”, US Patent 7,071,066, Jul. 4, 2006.

  8. T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual-gate structure and method of fabricating integrated circuits having dual-gate structures”, US Patent 7,030,024, Apr. 18, 2006

  9. T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual gate dielectric scheme: SiON for high performance devices and high k for low power device”, US Patent 6,890,811, May. 10, 2005.

  10. L. G. Yao, M. F. Wang, Y. M. Lin, T. H. Hou, and S. C. Chen, “Chemical vapor deposition (CVD) method employing wetting pre-treatment”, US Patent 6,764,927, Jul. 20, 2004

  11. Y. M. Lin, and T. H. Hou, “Layer of high-k inter-poly dielectric”, US Patent 6,753,224, Jun. 22, 2004.

  12. T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual gate dielectric scheme: SiON for high performance devices and high k for low power device”, US Patent 6,706,581, Mar. 16, 2004.



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